board/freescale/mpc8572ds/mpc8572ds.c

   1 /*
   2  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <asm/fsl_serdes.h>
  34 #include <miiphy.h>
  35 #include <libfdt.h>
  36 #include <fdt_support.h>
  37 #include <tsec.h>
  38 #include <netdev.h>
  39
  40 #include "../common/sgmii_riser.h"
  41
  42 long int fixed_sdram(void);
  43
  44 int checkboard (void)
  45 {
  46         u8 vboot;
  47         u8 *pixis_base = (u8 *)PIXIS_BASE;
  48
  49         puts ("Board: MPC8572DS ");
  50 #ifdef CONFIG_PHYS_64BIT
  51         puts ("(36-bit addrmap) ");
  52 #endif
  53         printf ("Sys ID: 0x%02x, "
  54                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  55                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  56                 in_8(pixis_base + PIXIS_PVER));
  57
  58         vboot = in_8(pixis_base + PIXIS_VBOOT);
  59         switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
  60                 case PIXIS_VBOOT_LBMAP_NOR0:
  61                         puts ("vBank: 0\n");
  62                         break;
  63                 case PIXIS_VBOOT_LBMAP_PJET:
  64                         puts ("Promjet\n");
  65                         break;
  66                 case PIXIS_VBOOT_LBMAP_NAND:
  67                         puts ("NAND\n");
  68                         break;
  69                 case PIXIS_VBOOT_LBMAP_NOR1:
  70                         puts ("vBank: 1\n");
  71                         break;
  72         }
  73
  74         return 0;
  75 }
  76
  77 phys_size_t initdram(int board_type)
  78 {
  79         phys_size_t dram_size = 0;
  80
  81         puts("Initializing....");
  82
  83 #ifdef CONFIG_SPD_EEPROM
  84         dram_size = fsl_ddr_sdram();
  85 #else
  86         dram_size = fixed_sdram();
  87 #endif
  88         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  89         dram_size *= 0x100000;
  90
  91         puts("    DDR: ");
  92         return dram_size;
  93 }
  94
  95 #if !defined(CONFIG_SPD_EEPROM)
  96 /*
  97  * Fixed sdram init -- doesn't use serial presence detect.
  98  */
  99
 100 phys_size_t fixed_sdram (void)
 101 {
 102         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 103         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 104         uint d_init;
 105
 106         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 107         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 108
 109         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 110         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 111         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 112         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 113         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 114         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 115         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 116         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 117         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 118         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 119
 120 #if defined (CONFIG_DDR_ECC)
 121         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 122         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 123         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 124 #endif
 125         asm("sync;isync");
 126
 127         udelay(500);
 128
 129         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 130
 131 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 132         d_init = 1;
 133         debug("DDR - 1st controller: memory initializing\n");
 134         /*
 135          * Poll until memory is initialized.
 136          * 512 Meg at 400 might hit this 200 times or so.
 137          */
 138         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 139                 udelay(1000);
 140         }
 141         debug("DDR: memory initialized\n\n");
 142         asm("sync; isync");
 143         udelay(500);
 144 #endif
 145
 146         return 512 * 1024 * 1024;
 147 }
 148
 149 #endif
 150
 151 #ifdef CONFIG_PCIE1
 152 static struct pci_controller pcie1_hose;
 153 #endif
 154
 155 #ifdef CONFIG_PCIE2
 156 static struct pci_controller pcie2_hose;
 157 #endif
 158
 159 #ifdef CONFIG_PCIE3
 160 static struct pci_controller pcie3_hose;
 161 #endif
 162
 163 #ifdef CONFIG_PCI
 164 void pci_init_board(void)
 165 {
 166         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 167         struct fsl_pci_info pci_info[3];
 168         u32 devdisr, pordevsr, io_sel, temp32;
 169         int first_free_busno = 0;
 170         int num = 0;
 171
 172         int pcie_ep, pcie_configured;
 173
 174         devdisr = in_be32(&gur->devdisr);
 175         pordevsr = in_be32(&gur->pordevsr);
 176         io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 177
 178         debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 179
 180         puts("\n");
 181 #ifdef CONFIG_PCIE3
 182         pcie_configured = is_serdes_configured(PCIE3);
 183
 184         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
 185                 SET_STD_PCIE_INFO(pci_info[num], 3);
 186                 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 187                 printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
 188                         pcie_ep ? "Endpoint" : "Root Complex",
 189                         pci_info[num].regs);
 190                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 191                                         &pcie3_hose, first_free_busno);
 192                 /*
 193                  * Activate ULI1575 legacy chip by performing a fake
 194                  * memory access.  Needed to make ULI RTC work.
 195                  * Device 1d has the first on-board memory BAR.
 196                  */
 197                 pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0),
 198                                 PCI_BASE_ADDRESS_1, &temp32);
 199                 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 200                         void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 201                                         temp32, 4, 0);
 202                         debug(" uli1572 read to %p\n", p);
 203                         in_be32(p);
 204                 }
 205         } else {
 206                 printf("PCIE3: disabled\n");
 207         }
 208         puts("\n");
 209 #else
 210         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
 211 #endif
 212
 213 #ifdef CONFIG_PCIE2
 214         pcie_configured = is_serdes_configured(PCIE2);
 215
 216         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
 217                 SET_STD_PCIE_INFO(pci_info[num], 2);
 218                 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 219                 printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
 220                         pcie_ep ? "Endpoint" : "Root Complex",
 221                         pci_info[num].regs);
 222                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 223                                         &pcie2_hose, first_free_busno);
 224         } else {
 225                 printf("PCIE2: disabled\n");
 226         }
 227
 228         puts("\n");
 229 #else
 230         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
 231 #endif
 232
 233 #ifdef CONFIG_PCIE1
 234         pcie_configured = is_serdes_configured(PCIE1);
 235
 236         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 237                 SET_STD_PCIE_INFO(pci_info[num], 1);
 238                 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 239                 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
 240                                 pcie_ep ? "Endpoint" : "Root Complex",
 241                                 pci_info[num].regs);
 242                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 243                                         &pcie1_hose, first_free_busno);
 244         } else {
 245                 printf("PCIE1: disabled\n");
 246         }
 247
 248         puts("\n");
 249 #else
 250         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
 251 #endif
 252 }
 253 #endif
 254
 255 int board_early_init_r(void)
 256 {
 257         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 258         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 259
 260         /*
 261          * Remap Boot flash + PROMJET region to caching-inhibited
 262          * so that flash can be erased properly.
 263          */
 264
 265         /* Flush d-cache and invalidate i-cache of any FLASH data */
 266         flush_dcache();
 267         invalidate_icache();
 268
 269         /* invalidate existing TLB entry for flash + promjet */
 270         disable_tlb(flash_esel);
 271
 272         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,       /* tlb, epn, rpn */
 273                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 274                         0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 275
 276         return 0;
 277 }
 278
 279 #ifdef CONFIG_TSEC_ENET
 280 int board_eth_init(bd_t *bis)
 281 {
 282         struct tsec_info_struct tsec_info[4];
 283         int num = 0;
 284
 285 #ifdef CONFIG_TSEC1
 286         SET_STD_TSEC_INFO(tsec_info[num], 1);
 287         if (is_serdes_configured(SGMII_TSEC1)) {
 288                 puts("eTSEC1 is in sgmii mode.\n");
 289                 tsec_info[num].flags |= TSEC_SGMII;
 290         }
 291         num++;
 292 #endif
 293 #ifdef CONFIG_TSEC2
 294         SET_STD_TSEC_INFO(tsec_info[num], 2);
 295         if (is_serdes_configured(SGMII_TSEC2)) {
 296                 puts("eTSEC2 is in sgmii mode.\n");
 297                 tsec_info[num].flags |= TSEC_SGMII;
 298         }
 299         num++;
 300 #endif
 301 #ifdef CONFIG_TSEC3
 302         SET_STD_TSEC_INFO(tsec_info[num], 3);
 303         if (is_serdes_configured(SGMII_TSEC3)) {
 304                 puts("eTSEC3 is in sgmii mode.\n");
 305                 tsec_info[num].flags |= TSEC_SGMII;
 306         }
 307         num++;
 308 #endif
 309 #ifdef CONFIG_TSEC4
 310         SET_STD_TSEC_INFO(tsec_info[num], 4);
 311         if (is_serdes_configured(SGMII_TSEC4)) {
 312                 puts("eTSEC4 is in sgmii mode.\n");
 313                 tsec_info[num].flags |= TSEC_SGMII;
 314         }
 315         num++;
 316 #endif
 317
 318         if (!num) {
 319                 printf("No TSECs initialized\n");
 320
 321                 return 0;
 322         }
 323
 324 #ifdef CONFIG_FSL_SGMII_RISER
 325         fsl_sgmii_riser_init(tsec_info, num);
 326 #endif
 327
 328         tsec_eth_init(bis, tsec_info, num);
 329
 330         return pci_eth_init(bis);
 331 }
 332 #endif
 333
 334 #if defined(CONFIG_OF_BOARD_SETUP)
 335 void ft_board_setup(void *blob, bd_t *bd)
 336 {
 337         phys_addr_t base;
 338         phys_size_t size;
 339
 340         ft_cpu_setup(blob, bd);
 341
 342         base = getenv_bootm_low();
 343         size = getenv_bootm_size();
 344
 345         fdt_fixup_memory(blob, (u64)base, (u64)size);
 346
 347         FT_FSL_PCI_SETUP;
 348
 349 #ifdef CONFIG_FSL_SGMII_RISER
 350         fsl_sgmii_riser_fdt_fixup(blob);
 351 #endif
 352 }
 353 #endif
 354
 355 #ifdef CONFIG_MP
 356 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 357
 358 void board_lmb_reserve(struct lmb *lmb)
 359 {
 360         cpu_mp_lmb_reserve(lmb);
 361 }
 362 #endif