2 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
35 #include <fdt_support.h>
38 #include "../common/pixis.h"
39 #include "../common/sgmii_riser.h"
41 long int fixed_sdram(void);
46 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
48 puts ("Board: MPC8572DS ");
49 #ifdef CONFIG_PHYS_64BIT
50 puts ("(36-bit addrmap) ");
52 printf ("Sys ID: 0x%02x, "
53 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
54 in_8(pixis_base
+ PIXIS_ID
), in_8(pixis_base
+ PIXIS_VER
),
55 in_8(pixis_base
+ PIXIS_PVER
));
57 vboot
= in_8(pixis_base
+ PIXIS_VBOOT
);
58 switch ((vboot
& PIXIS_VBOOT_LBMAP
) >> 6) {
59 case PIXIS_VBOOT_LBMAP_NOR0
:
62 case PIXIS_VBOOT_LBMAP_PJET
:
65 case PIXIS_VBOOT_LBMAP_NAND
:
68 case PIXIS_VBOOT_LBMAP_NOR1
:
76 phys_size_t
initdram(int board_type
)
78 phys_size_t dram_size
= 0;
80 puts("Initializing....");
82 #ifdef CONFIG_SPD_EEPROM
83 dram_size
= fsl_ddr_sdram();
85 dram_size
= fixed_sdram();
87 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
88 dram_size
*= 0x100000;
94 #if !defined(CONFIG_SPD_EEPROM)
96 * Fixed sdram init -- doesn't use serial presence detect.
99 phys_size_t
fixed_sdram (void)
101 volatile immap_t
*immap
= (immap_t
*)CONFIG_SYS_IMMR
;
102 volatile ccsr_ddr_t
*ddr
= &immap
->im_ddr
;
105 ddr
->cs0_bnds
= CONFIG_SYS_DDR_CS0_BNDS
;
106 ddr
->cs0_config
= CONFIG_SYS_DDR_CS0_CONFIG
;
108 ddr
->timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
109 ddr
->timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
110 ddr
->timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
111 ddr
->timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
112 ddr
->sdram_mode
= CONFIG_SYS_DDR_MODE_1
;
113 ddr
->sdram_mode_2
= CONFIG_SYS_DDR_MODE_2
;
114 ddr
->sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
115 ddr
->sdram_data_init
= CONFIG_SYS_DDR_DATA_INIT
;
116 ddr
->sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL
;
117 ddr
->sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL2
;
119 #if defined (CONFIG_DDR_ECC)
120 ddr
->err_int_en
= CONFIG_SYS_DDR_ERR_INT_EN
;
121 ddr
->err_disable
= CONFIG_SYS_DDR_ERR_DIS
;
122 ddr
->err_sbe
= CONFIG_SYS_DDR_SBE
;
128 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CONTROL
;
130 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
132 debug("DDR - 1st controller: memory initializing\n");
134 * Poll until memory is initialized.
135 * 512 Meg at 400 might hit this 200 times or so.
137 while ((ddr
->sdram_cfg_2
& (d_init
<< 4)) != 0) {
140 debug("DDR: memory initialized\n\n");
145 return 512 * 1024 * 1024;
151 static struct pci_controller pcie1_hose
;
155 static struct pci_controller pcie2_hose
;
159 static struct pci_controller pcie3_hose
;
162 int first_free_busno
=0;
164 void pci_init_board(void)
166 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
167 uint devdisr
= gur
->devdisr
;
168 uint io_sel
= (gur
->pordevsr
& MPC85xx_PORDEVSR_IO_SEL
) >> 19;
169 uint host_agent
= (gur
->porbmsr
& MPC85xx_PORBMSR_HA
) >> 16;
171 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
172 devdisr
, io_sel
, host_agent
);
174 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII1_DIS
))
175 printf (" eTSEC1 is in sgmii mode.\n");
176 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII2_DIS
))
177 printf (" eTSEC2 is in sgmii mode.\n");
178 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII3_DIS
))
179 printf (" eTSEC3 is in sgmii mode.\n");
180 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII4_DIS
))
181 printf (" eTSEC4 is in sgmii mode.\n");
186 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE3_ADDR
;
187 struct pci_controller
*hose
= &pcie3_hose
;
188 int pcie_ep
= (host_agent
== 0) || (host_agent
== 3) ||
189 (host_agent
== 5) || (host_agent
== 6);
190 int pcie_configured
= (io_sel
== 0x7);
191 struct pci_region
*r
= hose
->regions
;
194 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE3
)){
195 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
196 pcie_ep
? "End Point" : "Root Complex",
198 if (pci
->pme_msg_det
) {
199 pci
->pme_msg_det
= 0xffffffff;
200 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
205 r
+= fsl_pci_setup_inbound_windows(r
);
207 /* outbound memory */
209 CONFIG_SYS_PCIE3_MEM_BUS
,
210 CONFIG_SYS_PCIE3_MEM_PHYS
,
211 CONFIG_SYS_PCIE3_MEM_SIZE
,
216 CONFIG_SYS_PCIE3_IO_BUS
,
217 CONFIG_SYS_PCIE3_IO_PHYS
,
218 CONFIG_SYS_PCIE3_IO_SIZE
,
221 hose
->region_count
= r
- hose
->regions
;
222 hose
->first_busno
=first_free_busno
;
223 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
227 first_free_busno
=hose
->last_busno
+1;
228 printf (" PCIE3 on bus %02x - %02x\n",
229 hose
->first_busno
,hose
->last_busno
);
232 * Activate ULI1575 legacy chip by performing a fake
233 * memory access. Needed to make ULI RTC work.
234 * Device 1d has the first on-board memory BAR.
237 pci_hose_read_config_dword(hose
, PCI_BDF(2, 0x1d, 0 ),
238 PCI_BASE_ADDRESS_1
, &temp32
);
239 if (temp32
>= CONFIG_SYS_PCIE3_MEM_BUS
) {
240 void *p
= pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
242 debug(" uli1572 read to %p\n", p
);
246 printf (" PCIE3: disabled\n");
251 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE3
; /* disable */
256 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE2_ADDR
;
257 struct pci_controller
*hose
= &pcie2_hose
;
258 int pcie_ep
= (host_agent
== 2) || (host_agent
== 4) ||
259 (host_agent
== 6) || (host_agent
== 0);
260 int pcie_configured
= (io_sel
== 0x3) || (io_sel
== 0x7);
261 struct pci_region
*r
= hose
->regions
;
263 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE2
)){
264 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
265 pcie_ep
? "End Point" : "Root Complex",
267 if (pci
->pme_msg_det
) {
268 pci
->pme_msg_det
= 0xffffffff;
269 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
274 r
+= fsl_pci_setup_inbound_windows(r
);
276 /* outbound memory */
278 CONFIG_SYS_PCIE2_MEM_BUS
,
279 CONFIG_SYS_PCIE2_MEM_PHYS
,
280 CONFIG_SYS_PCIE2_MEM_SIZE
,
285 CONFIG_SYS_PCIE2_IO_BUS
,
286 CONFIG_SYS_PCIE2_IO_PHYS
,
287 CONFIG_SYS_PCIE2_IO_SIZE
,
290 hose
->region_count
= r
- hose
->regions
;
291 hose
->first_busno
=first_free_busno
;
292 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
295 first_free_busno
=hose
->last_busno
+1;
296 printf (" PCIE2 on bus %02x - %02x\n",
297 hose
->first_busno
,hose
->last_busno
);
300 printf (" PCIE2: disabled\n");
305 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE2
; /* disable */
309 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CONFIG_SYS_PCIE1_ADDR
;
310 struct pci_controller
*hose
= &pcie1_hose
;
311 int pcie_ep
= (host_agent
<= 1) || (host_agent
== 4) ||
313 int pcie_configured
= (io_sel
== 0x2) || (io_sel
== 0x3) ||
314 (io_sel
== 0x7) || (io_sel
== 0xb) ||
315 (io_sel
== 0xc) || (io_sel
== 0xf);
316 struct pci_region
*r
= hose
->regions
;
318 if (pcie_configured
&& !(devdisr
& MPC85xx_DEVDISR_PCIE
)){
319 printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
320 pcie_ep
? "End Point" : "Root Complex",
322 if (pci
->pme_msg_det
) {
323 pci
->pme_msg_det
= 0xffffffff;
324 debug (" with errors. Clearing. Now 0x%08x",pci
->pme_msg_det
);
329 r
+= fsl_pci_setup_inbound_windows(r
);
331 /* outbound memory */
333 CONFIG_SYS_PCIE1_MEM_BUS
,
334 CONFIG_SYS_PCIE1_MEM_PHYS
,
335 CONFIG_SYS_PCIE1_MEM_SIZE
,
340 CONFIG_SYS_PCIE1_IO_BUS
,
341 CONFIG_SYS_PCIE1_IO_PHYS
,
342 CONFIG_SYS_PCIE1_IO_SIZE
,
345 hose
->region_count
= r
- hose
->regions
;
346 hose
->first_busno
=first_free_busno
;
348 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
352 first_free_busno
=hose
->last_busno
+1;
353 printf(" PCIE1 on bus %02x - %02x\n",
354 hose
->first_busno
,hose
->last_busno
);
357 printf (" PCIE1: disabled\n");
362 gur
->devdisr
|= MPC85xx_DEVDISR_PCIE
; /* disable */
367 int board_early_init_r(void)
369 const unsigned int flashbase
= CONFIG_SYS_FLASH_BASE
;
370 const u8 flash_esel
= 2;
373 * Remap Boot flash + PROMJET region to caching-inhibited
374 * so that flash can be erased properly.
377 /* Flush d-cache and invalidate i-cache of any FLASH data */
381 /* invalidate existing TLB entry for flash + promjet */
382 disable_tlb(flash_esel
);
384 set_tlb(1, flashbase
, CONFIG_SYS_FLASH_BASE_PHYS
, /* tlb, epn, rpn */
385 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
, /* perms, wimge */
386 0, flash_esel
, BOOKE_PAGESZ_256M
, 1); /* ts, esel, tsize, iprot */
391 #ifdef CONFIG_GET_CLK_FROM_ICS307
392 /* decode S[0-2] to Output Divider (OD) */
393 static unsigned char ics307_S_to_OD
[] = {
394 10, 2, 8, 4, 5, 7, 3, 6
397 /* Calculate frequency being generated by ICS307-02 clock chip based upon
398 * the control bytes being programmed into it. */
399 /* XXX: This function should probably go into a common library */
401 ics307_clk_freq (unsigned char cw0
, unsigned char cw1
, unsigned char cw2
)
403 const unsigned long InputFrequency
= CONFIG_ICS307_REFCLK_HZ
;
404 unsigned long VDW
= ((cw1
<< 1) & 0x1FE) + ((cw2
>> 7) & 1);
405 unsigned long RDW
= cw2
& 0x7F;
406 unsigned long OD
= ics307_S_to_OD
[cw0
& 0x7];
409 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
411 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
412 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
413 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
415 * R6:R0 = Reference Divider Word (RDW)
416 * V8:V0 = VCO Divider Word (VDW)
417 * S2:S0 = Output Divider Select (OD)
418 * F1:F0 = Function of CLK2 Output
420 * C1:C0 = internal load capacitance for cyrstal
423 /* Adding 1 to get a "nicely" rounded number, but this needs
424 * more tweaking to get a "properly" rounded number. */
426 freq
= 1 + (InputFrequency
* 2 * (VDW
+ 8) / ((RDW
+ 2) * OD
));
428 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0
, cw1
, cw2
,
433 unsigned long get_board_sys_clk(ulong dummy
)
435 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
437 return ics307_clk_freq (
438 in_8(pixis_base
+ PIXIS_VSYSCLK0
),
439 in_8(pixis_base
+ PIXIS_VSYSCLK1
),
440 in_8(pixis_base
+ PIXIS_VSYSCLK2
)
444 unsigned long get_board_ddr_clk(ulong dummy
)
446 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
448 return ics307_clk_freq (
449 in_8(pixis_base
+ PIXIS_VDDRCLK0
),
450 in_8(pixis_base
+ PIXIS_VDDRCLK1
),
451 in_8(pixis_base
+ PIXIS_VDDRCLK2
)
455 unsigned long get_board_sys_clk(ulong dummy
)
459 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
461 i
= in_8(pixis_base
+ PIXIS_SPD
);
494 unsigned long get_board_ddr_clk(ulong dummy
)
498 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
500 i
= in_8(pixis_base
+ PIXIS_SPD
);
534 #ifdef CONFIG_TSEC_ENET
535 int board_eth_init(bd_t
*bis
)
537 struct tsec_info_struct tsec_info
[4];
538 volatile ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
542 SET_STD_TSEC_INFO(tsec_info
[num
], 1);
543 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII1_DIS
))
544 tsec_info
[num
].flags
|= TSEC_SGMII
;
548 SET_STD_TSEC_INFO(tsec_info
[num
], 2);
549 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII2_DIS
))
550 tsec_info
[num
].flags
|= TSEC_SGMII
;
554 SET_STD_TSEC_INFO(tsec_info
[num
], 3);
555 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII3_DIS
))
556 tsec_info
[num
].flags
|= TSEC_SGMII
;
560 SET_STD_TSEC_INFO(tsec_info
[num
], 4);
561 if (!(gur
->pordevsr
& MPC85xx_PORDEVSR_SGMII4_DIS
))
562 tsec_info
[num
].flags
|= TSEC_SGMII
;
567 printf("No TSECs initialized\n");
572 #ifdef CONFIG_FSL_SGMII_RISER
573 fsl_sgmii_riser_init(tsec_info
, num
);
576 tsec_eth_init(bis
, tsec_info
, num
);
582 #if defined(CONFIG_OF_BOARD_SETUP)
583 void ft_board_setup(void *blob
, bd_t
*bd
)
588 ft_cpu_setup(blob
, bd
);
590 base
= getenv_bootm_low();
591 size
= getenv_bootm_size();
593 fdt_fixup_memory(blob
, (u64
)base
, (u64
)size
);
596 ft_fsl_pci_setup(blob
, "pci0", &pcie3_hose
);
599 ft_fsl_pci_setup(blob
, "pci1", &pcie2_hose
);
602 ft_fsl_pci_setup(blob
, "pci2", &pcie1_hose
);
604 #ifdef CONFIG_FSL_SGMII_RISER
605 fsl_sgmii_riser_fdt_fixup(blob
);
611 extern void cpu_mp_lmb_reserve(struct lmb
*lmb
);
613 void board_lmb_reserve(struct lmb
*lmb
)
615 cpu_mp_lmb_reserve(lmb
);