board/freescale/mpc8610hpcd/mpc8610hpcd.c

   1 /*
   2  * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_86xx.h>
  28 #include <asm/fsl_pci.h>
  29 #include <asm/fsl_ddr_sdram.h>
  30 #include <asm/fsl_serdes.h>
  31 #include <i2c.h>
  32 #include <asm/io.h>
  33 #include <libfdt.h>
  34 #include <fdt_support.h>
  35 #include <spd_sdram.h>
  36 #include <netdev.h>
  37
  38 void sdram_init(void);
  39 phys_size_t fixed_sdram(void);
  40 int mpc8610hpcd_diu_init(void);
  41
  42
  43 /* called before any console output */
  44 int board_early_init_f(void)
  45 {
  46         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  47         volatile ccsr_gur_t *gur = &immap->im_gur;
  48
  49         gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
  50
  51         return 0;
  52 }
  53
  54 int misc_init_r(void)
  55 {
  56         u8 tmp_val, version;
  57         u8 *pixis_base = (u8 *)PIXIS_BASE;
  58
  59         /*Do not use 8259PIC*/
  60         tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  61         out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
  62
  63         /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
  64         version = in_8(pixis_base + PIXIS_PVER);
  65         if(version >= 0x07) {
  66                 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  67                 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
  68         }
  69
  70         /* Using this for DIU init before the driver in linux takes over
  71          *  Enable the TFP410 Encoder (I2C address 0x38)
  72          */
  73
  74         tmp_val = 0xBF;
  75         i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  76         /* Verify if enabled */
  77         tmp_val = 0;
  78         i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  79         debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
  80
  81         tmp_val = 0x10;
  82         i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  83         /* Verify if enabled */
  84         tmp_val = 0;
  85         i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  86         debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
  87
  88         return 0;
  89 }
  90
  91 int checkboard(void)
  92 {
  93         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  94         volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
  95         u8 *pixis_base = (u8 *)PIXIS_BASE;
  96
  97         printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
  98                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  99                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
 100                 in_8(pixis_base + PIXIS_PVER));
 101
 102         /*
 103          * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
 104          * bank and LBMAP=00 is the alternate bank.  However, the pixis
 105          * altbank code can only set bits, not clear them, so we treat 00 as
 106          * the normal bank and 11 as the alternate.
 107          */
 108         switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
 109         case 0:
 110                 puts("vBank: Standard\n");
 111                 break;
 112         case 0x40:
 113                 puts("Promjet\n");
 114                 break;
 115         case 0x80:
 116                 puts("NAND\n");
 117                 break;
 118         case 0xC0:
 119                 puts("vBank: Alternate\n");
 120                 break;
 121         }
 122
 123         mcm->abcr |= 0x00010000; /* 0 */
 124         mcm->hpmr3 = 0x80000008; /* 4c */
 125         mcm->hpmr0 = 0;
 126         mcm->hpmr1 = 0;
 127         mcm->hpmr2 = 0;
 128         mcm->hpmr4 = 0;
 129         mcm->hpmr5 = 0;
 130
 131         return 0;
 132 }
 133
 134
 135 phys_size_t
 136 initdram(int board_type)
 137 {
 138         phys_size_t dram_size = 0;
 139
 140 #if defined(CONFIG_SPD_EEPROM)
 141         dram_size = fsl_ddr_sdram();
 142 #else
 143         dram_size = fixed_sdram();
 144 #endif
 145
 146         setup_ddr_bat(dram_size);
 147
 148         debug(" DDR: ");
 149         return dram_size;
 150 }
 151
 152
 153 #if !defined(CONFIG_SPD_EEPROM)
 154 /*
 155  * Fixed sdram init -- doesn't use serial presence detect.
 156  */
 157
 158 phys_size_t fixed_sdram(void)
 159 {
 160 #if !defined(CONFIG_SYS_RAMBOOT)
 161         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 162         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 163         uint d_init;
 164
 165         ddr->cs0_bnds = 0x0000001f;
 166         ddr->cs0_config = 0x80010202;
 167
 168         ddr->timing_cfg_3 = 0x00000000;
 169         ddr->timing_cfg_0 = 0x00260802;
 170         ddr->timing_cfg_1 = 0x3935d322;
 171         ddr->timing_cfg_2 = 0x14904cc8;
 172         ddr->sdram_mode = 0x00480432;
 173         ddr->sdram_mode_2 = 0x00000000;
 174         ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
 175         ddr->sdram_data_init = 0xDEADBEEF;
 176         ddr->sdram_clk_cntl = 0x03800000;
 177         ddr->sdram_cfg_2 = 0x04400010;
 178
 179 #if defined(CONFIG_DDR_ECC)
 180         ddr->err_int_en = 0x0000000d;
 181         ddr->err_disable = 0x00000000;
 182         ddr->err_sbe = 0x00010000;
 183 #endif
 184         asm("sync;isync");
 185
 186         udelay(500);
 187
 188         ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
 189
 190
 191 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 192         d_init = 1;
 193         debug("DDR - 1st controller: memory initializing\n");
 194         /*
 195          * Poll until memory is initialized.
 196          * 512 Meg at 400 might hit this 200 times or so.
 197          */
 198         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 199                 udelay(1000);
 200
 201         debug("DDR: memory initialized\n\n");
 202         asm("sync; isync");
 203         udelay(500);
 204 #endif
 205
 206         return 512 * 1024 * 1024;
 207 #endif
 208         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 209 }
 210
 211 #endif
 212
 213 #if defined(CONFIG_PCI)
 214 /*
 215  * Initialize PCI Devices, report devices found.
 216  */
 217
 218 #ifndef CONFIG_PCI_PNP
 219 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 220         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 221          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 222          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 223                                  PCI_ENET0_MEMADDR,
 224                                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
 225         {}
 226 };
 227 #endif
 228
 229
 230 static struct pci_controller pci1_hose = {
 231 #ifndef CONFIG_PCI_PNP
 232 config_table:pci_mpc86xxcts_config_table
 233 #endif
 234 };
 235 #endif /* CONFIG_PCI */
 236
 237 void pci_init_board(void)
 238 {
 239         volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 240         volatile ccsr_gur_t *gur = &immap->im_gur;
 241         struct fsl_pci_info pci_info;
 242         u32 devdisr, pordevsr;
 243         int first_free_busno;
 244         int pci_agent;
 245
 246         devdisr = in_be32(&gur->devdisr);
 247         pordevsr = in_be32(&gur->pordevsr);
 248
 249         first_free_busno = fsl_pcie_init_board(0);
 250
 251 #ifdef CONFIG_PCI1
 252         if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
 253                 SET_STD_PCI_INFO(pci_info, 1);
 254                 set_next_law(pci_info.mem_phys,
 255                         law_size_bits(pci_info.mem_size), pci_info.law);
 256                 set_next_law(pci_info.io_phys,
 257                         law_size_bits(pci_info.io_size), pci_info.law);
 258
 259                 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 260                 printf("PCI: connected to PCI slots as %s" \
 261                         " (base address %lx)\n",
 262                         pci_agent ? "Agent" : "Host",
 263                         pci_info.regs);
 264                 first_free_busno = fsl_pci_init_port(&pci_info,
 265                                         &pci1_hose, first_free_busno);
 266         } else {
 267                 printf("PCI: disabled\n");
 268         }
 269
 270         puts("\n");
 271 #else
 272         setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
 273 #endif
 274
 275         fsl_pcie_init_board(first_free_busno);
 276 }
 277
 278 #if defined(CONFIG_OF_BOARD_SETUP)
 279 void
 280 ft_board_setup(void *blob, bd_t *bd)
 281 {
 282         ft_cpu_setup(blob, bd);
 283
 284         FT_FSL_PCI_SETUP;
 285 }
 286 #endif
 287
 288 /*
 289  * get_board_sys_clk
 290  * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 291  */
 292
 293 unsigned long
 294 get_board_sys_clk(ulong dummy)
 295 {
 296         u8 i;
 297         ulong val = 0;
 298         u8 *pixis_base = (u8 *)PIXIS_BASE;
 299
 300         i = in_8(pixis_base + PIXIS_SPD);
 301         i &= 0x07;
 302
 303         switch (i) {
 304         case 0:
 305                 val = 33333000;
 306                 break;
 307         case 1:
 308                 val = 39999600;
 309                 break;
 310         case 2:
 311                 val = 49999500;
 312                 break;
 313         case 3:
 314                 val = 66666000;
 315                 break;
 316         case 4:
 317                 val = 83332500;
 318                 break;
 319         case 5:
 320                 val = 99999000;
 321                 break;
 322         case 6:
 323                 val = 133332000;
 324                 break;
 325         case 7:
 326                 val = 166665000;
 327                 break;
 328         }
 329
 330         return val;
 331 }
 332
 333 int board_eth_init(bd_t *bis)
 334 {
 335         return pci_eth_init(bis);
 336 }
 337
 338 void board_reset(void)
 339 {
 340         u8 *pixis_base = (u8 *)PIXIS_BASE;
 341
 342         out_8(pixis_base + PIXIS_RST, 0);
 343
 344         while (1)
 345                 ;
 346 }