board/freescale/mpc8610hpcd/mpc8610hpcd.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #define DEBUG
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_86xx.h>
  28 #include <asm/immap_fsl_pci.h>
  29 #include <spd.h>
  30 #include <asm/io.h>
  31
  32
  33 #if defined(CONFIG_OF_FLAT_TREE)
  34 #include <ft_build.h>
  35 extern void ft_cpu_setup(void *blob, bd_t *bd);
  36 #endif
  37
  38 #include "../common/pixis.h"
  39
  40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  41 extern void ddr_enable_ecc(unsigned int dram_size);
  42 #endif
  43
  44 #if defined(CONFIG_SPD_EEPROM)
  45 #include "spd_sdram.h"
  46 #endif
  47
  48 void sdram_init(void);
  49 long int fixed_sdram(void);
  50
  51 /* called before any console output */
  52 int board_early_init_f(void)
  53 {
  54         volatile immap_t *immap = (immap_t *)CFG_IMMR;
  55         volatile ccsr_gur_t *gur = &immap->im_gur;
  56
  57         gur->gpiocr |= 0x888a5500; /* DIU16, IR1, UART0, UART2 */
  58
  59         return 0;
  60 }
  61
  62 int checkboard(void)
  63 {
  64         volatile immap_t *immap = (immap_t *)CFG_IMMR;
  65         volatile ccsr_lbc_t *memctl = &immap->im_lbc;
  66         volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
  67
  68         puts("Board: MPC8610HPCD\n");
  69
  70         mcm->abcr |= 0x00010000; /* 0 */
  71         mcm->hpmr3 = 0x80000008; /* 4c */
  72         mcm->hpmr0 = 0;
  73         mcm->hpmr1 = 0;
  74         mcm->hpmr2 = 0;
  75         mcm->hpmr4 = 0;
  76         mcm->hpmr5 = 0;
  77
  78         return 0;
  79 }
  80
  81
  82 long int
  83 initdram(int board_type)
  84 {
  85         long dram_size = 0;
  86
  87 #if defined(CONFIG_SPD_EEPROM)
  88         dram_size = spd_sdram();
  89 #else
  90         dram_size = fixed_sdram();
  91 #endif
  92
  93 #if defined(CFG_RAMBOOT)
  94         puts(" DDR: ");
  95         return dram_size;
  96 #endif
  97
  98 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  99         /*
 100          * Initialize and enable DDR ECC.
 101          */
 102         ddr_enable_ecc(dram_size);
 103 #endif
 104
 105         puts(" DDR: ");
 106         return dram_size;
 107 }
 108
 109
 110 #if defined(CFG_DRAM_TEST)
 111 int
 112 testdram(void)
 113 {
 114         uint *pstart = (uint *) CFG_MEMTEST_START;
 115         uint *pend = (uint *) CFG_MEMTEST_END;
 116         uint *p;
 117
 118         puts("SDRAM test phase 1:\n");
 119         for (p = pstart; p < pend; p++)
 120                 *p = 0xaaaaaaaa;
 121
 122         for (p = pstart; p < pend; p++) {
 123                 if (*p != 0xaaaaaaaa) {
 124                         printf("SDRAM test fails at: %08x\n", (uint) p);
 125                         return 1;
 126                 }
 127         }
 128
 129         puts("SDRAM test phase 2:\n");
 130         for (p = pstart; p < pend; p++)
 131                 *p = 0x55555555;
 132
 133         for (p = pstart; p < pend; p++) {
 134                 if (*p != 0x55555555) {
 135                         printf("SDRAM test fails at: %08x\n", (uint) p);
 136                         return 1;
 137                 }
 138         }
 139
 140         puts("SDRAM test passed.\n");
 141         return 0;
 142 }
 143 #endif
 144
 145
 146 #if !defined(CONFIG_SPD_EEPROM)
 147 /*
 148  * Fixed sdram init -- doesn't use serial presence detect.
 149  */
 150
 151 long int fixed_sdram(void)
 152 {
 153 #if !defined(CFG_RAMBOOT)
 154         volatile immap_t *immap = (immap_t *)CFG_IMMR;
 155         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 156         uint d_init;
 157
 158         ddr->cs0_bnds = 0x0000001f;
 159         ddr->cs0_config = 0x80010202;
 160
 161         ddr->ext_refrec = 0x00000000;
 162         ddr->timing_cfg_0 = 0x00260802;
 163         ddr->timing_cfg_1 = 0x3935d322;
 164         ddr->timing_cfg_2 = 0x14904cc8;
 165         ddr->sdram_mode_1 = 0x00480432;
 166         ddr->sdram_mode_2 = 0x00000000;
 167         ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
 168         ddr->sdram_data_init = 0xDEADBEEF;
 169         ddr->sdram_clk_cntl = 0x03800000;
 170         ddr->sdram_cfg_2 = 0x04400010;
 171
 172 #if defined(CONFIG_DDR_ECC)
 173         ddr->err_int_en = 0x0000000d;
 174         ddr->err_disable = 0x00000000;
 175         ddr->err_sbe = 0x00010000;
 176 #endif
 177         asm("sync;isync");
 178
 179         udelay(500);
 180
 181         ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
 182
 183
 184 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 185         d_init = 1;
 186         debug("DDR - 1st controller: memory initializing\n");
 187         /*
 188          * Poll until memory is initialized.
 189          * 512 Meg at 400 might hit this 200 times or so.
 190          */
 191         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 192                 udelay(1000);
 193
 194         debug("DDR: memory initialized\n\n");
 195         asm("sync; isync");
 196         udelay(500);
 197 #endif
 198
 199         return 512 * 1024 * 1024;
 200 #endif
 201         return CFG_SDRAM_SIZE * 1024 * 1024;
 202 }
 203
 204 #endif
 205
 206 #if defined(CONFIG_PCI)
 207 /*
 208  * Initialize PCI Devices, report devices found.
 209  */
 210
 211 #ifndef CONFIG_PCI_PNP
 212 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 213         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 214          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 215          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 216                                  PCI_ENET0_MEMADDR,
 217                                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
 218         {}
 219 };
 220 #endif
 221
 222
 223 static struct pci_controller pci1_hose = {
 224 #ifndef CONFIG_PCI_PNP
 225 config_table:pci_mpc86xxcts_config_table
 226 #endif
 227 };
 228 #endif /* CONFIG_PCI */
 229
 230 #ifdef CONFIG_PCIE1
 231 static struct pci_controller pcie1_hose;
 232 #endif
 233
 234 #ifdef CONFIG_PCIE2
 235 static struct pci_controller pcie2_hose;
 236 #endif
 237
 238 int first_free_busno = 0;
 239
 240 void pci_init_board(void)
 241 {
 242         volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 243         volatile ccsr_gur_t *gur = &immap->im_gur;
 244         uint devdisr = gur->devdisr;
 245         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 246         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 247
 248         printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 249                 devdisr, io_sel, host_agent);
 250
 251
 252 #ifdef CONFIG_PCIE1
 253  {
 254         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 255         extern void fsl_pci_init(struct pci_controller *hose);
 256         struct pci_controller *hose = &pcie1_hose;
 257         int pcie_configured = (io_sel == 1) || (io_sel == 4);
 258         int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
 259                 (host_agent == 5);
 260
 261         if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
 262                 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
 263                         pcie_ep ? "End Point" : "Root Complex",
 264                         (uint)pci);
 265                 if (pci->pme_msg_det)
 266                         pci->pme_msg_det = 0xffffffff;
 267
 268                 /* inbound */
 269                 pci_set_region(hose->regions + 0,
 270                          CFG_PCI_MEMORY_BUS,
 271                          CFG_PCI_MEMORY_PHYS,
 272                          CFG_PCI_MEMORY_SIZE,
 273                          PCI_REGION_MEM | PCI_REGION_MEMORY);
 274
 275                 /* outbound memory */
 276                 pci_set_region(hose->regions + 1,
 277                          CFG_PCIE1_MEM_BASE,
 278                          CFG_PCIE1_MEM_PHYS,
 279                          CFG_PCIE1_MEM_SIZE,
 280                          PCI_REGION_MEM);
 281
 282                 /* outbound io */
 283                 pci_set_region(hose->regions + 2,
 284                          CFG_PCIE1_IO_BASE,
 285                          CFG_PCIE1_IO_PHYS,
 286                          CFG_PCIE1_IO_SIZE,
 287                          PCI_REGION_IO);
 288
 289                 hose->region_count = 3;
 290
 291                 hose->first_busno = first_free_busno;
 292                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 293                                  (int)&pci->cfg_data);
 294
 295                 fsl_pci_init(hose);
 296
 297                 first_free_busno = hose->last_busno + 1;
 298                 printf(" PCI-Express 1 on bus %02x - %02x\n",
 299                         hose->first_busno, hose->last_busno);
 300
 301         } else
 302                 puts(" PCI-Express 1: Disabled\n");
 303  }
 304 #else
 305         puts("PCI-Express 1: Disabled\n");
 306 #endif /* CONFIG_PCIE1 */
 307
 308
 309 #ifdef CONFIG_PCIE2
 310  {
 311         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
 312         extern void fsl_pci_init(struct pci_controller *hose);
 313         struct pci_controller *hose = &pcie2_hose;
 314
 315         int pcie_configured = (io_sel == 0) || (io_sel == 4);
 316         int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
 317                 (host_agent == 4);
 318
 319         if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
 320                 printf(" PCI-Express 2 connected to slot as %s" \
 321                         " (base address %x)\n",
 322                         pcie_ep ? "End Point" : "Root Complex",
 323                         (uint)pci);
 324                 if (pci->pme_msg_det)
 325                         pci->pme_msg_det = 0xffffffff;
 326
 327                 /* inbound */
 328                 pci_set_region(hose->regions + 0,
 329                          CFG_PCI_MEMORY_BUS,
 330                          CFG_PCI_MEMORY_PHYS,
 331                          CFG_PCI_MEMORY_SIZE,
 332                          PCI_REGION_MEM | PCI_REGION_MEMORY);
 333
 334                 /* outbound memory */
 335                 pci_set_region(hose->regions + 1,
 336                          CFG_PCIE2_MEM_BASE,
 337                          CFG_PCIE2_MEM_PHYS,
 338                          CFG_PCIE2_MEM_SIZE,
 339                          PCI_REGION_MEM);
 340
 341                 /* outbound io */
 342                 pci_set_region(hose->regions + 2,
 343                          CFG_PCIE2_IO_BASE,
 344                          CFG_PCIE2_IO_PHYS,
 345                          CFG_PCIE2_IO_SIZE,
 346                          PCI_REGION_IO);
 347
 348                 hose->region_count = 3;
 349
 350                 hose->first_busno = first_free_busno;
 351                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 352                                  (int)&pci->cfg_data);
 353
 354                 fsl_pci_init(hose);
 355
 356                 first_free_busno = hose->last_busno + 1;
 357                 printf(" PCI-Express 2 on bus %02x - %02x\n",
 358                         hose->first_busno, hose->last_busno);
 359         } else
 360                 puts(" PCI-Express 2: Disabled\n");
 361  }
 362 #else
 363         puts("PCI-Express 2: Disabled\n");
 364 #endif /* CONFIG_PCIE2 */
 365
 366
 367 #ifdef CONFIG_PCI1
 368  {
 369         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 370         extern void fsl_pci_init(struct pci_controller *hose);
 371         struct pci_controller *hose = &pci1_hose;
 372         int pci_agent = (host_agent >= 4) && (host_agent <= 6);
 373
 374         if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
 375                 printf(" PCI connected to PCI slots as %s" \
 376                         " (base address %x)\n",
 377                         pci_agent ? "Agent" : "Host",
 378                         (uint)pci);
 379
 380                 /* inbound */
 381                 pci_set_region(hose->regions + 0,
 382                          CFG_PCI_MEMORY_BUS,
 383                          CFG_PCI_MEMORY_PHYS,
 384                          CFG_PCI_MEMORY_SIZE,
 385                          PCI_REGION_MEM | PCI_REGION_MEMORY);
 386
 387                 /* outbound memory */
 388                 pci_set_region(hose->regions + 1,
 389                          CFG_PCI1_MEM_BASE,
 390                          CFG_PCI1_MEM_PHYS,
 391                          CFG_PCI1_MEM_SIZE,
 392                          PCI_REGION_MEM);
 393
 394                 /* outbound io */
 395                 pci_set_region(hose->regions + 2,
 396                          CFG_PCI1_IO_BASE,
 397                          CFG_PCI1_IO_PHYS,
 398                          CFG_PCI1_IO_SIZE,
 399                          PCI_REGION_IO);
 400
 401                 hose->region_count = 3;
 402
 403                 hose->first_busno = first_free_busno;
 404                 pci_setup_indirect(hose, (int) &pci->cfg_addr,
 405                                  (int) &pci->cfg_data);
 406
 407                 fsl_pci_init(hose);
 408
 409                 first_free_busno = hose->last_busno + 1;
 410                 printf(" PCI on bus %02x - %02x\n",
 411                         hose->first_busno, hose->last_busno);
 412
 413
 414         } else
 415                 puts(" PCI: Disabled\n");
 416  }
 417 #endif /* CONFIG_PCI1 */
 418 }
 419
 420 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 421 void
 422 ft_board_setup(void *blob, bd_t *bd)
 423 {
 424         u32 *p;
 425         int len;
 426
 427         ft_cpu_setup(blob, bd);
 428
 429         p = ft_get_prop(blob, "/memory/reg", &len);
 430         if (p != NULL) {
 431                 *p++ = cpu_to_be32(bd->bi_memstart);
 432                 *p = cpu_to_be32(bd->bi_memsize);
 433         }
 434
 435 #ifdef CONFIG_PCI1
 436         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
 437         if (p != NULL) {
 438                 p[0] = 0;
 439                 p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 440                 debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 441         }
 442 #endif
 443 #ifdef CONFIG_PCIE1
 444         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
 445         if (p != NULL) {
 446                 p[0] = 0;
 447                 p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 448                 debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 449         }
 450 #endif
 451 #ifdef CONFIG_PCIE2
 452         p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
 453         if (p != NULL) {
 454                 p[0] = 0;
 455                 p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 456                 debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
 457         }
 458 #endif
 459
 460 }
 461 #endif
 462
 463 /*
 464  * get_board_sys_clk
 465  * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 466  */
 467
 468 unsigned long
 469 get_board_sys_clk(ulong dummy)
 470 {
 471         u8 i, go_bit, rd_clks;
 472         ulong val = 0;
 473         ulong a;
 474
 475         a = PIXIS_BASE + PIXIS_SPD;
 476         i = in8(a);
 477         i &= 0x07;
 478
 479         switch (i) {
 480         case 0:
 481                 val = 33333000;
 482                 break;
 483         case 1:
 484                 val = 39999600;
 485                 break;
 486         case 2:
 487                 val = 49999500;
 488                 break;
 489         case 3:
 490                 val = 66666000;
 491                 break;
 492         case 4:
 493                 val = 83332500;
 494                 break;
 495         case 5:
 496                 val = 99999000;
 497                 break;
 498         case 6:
 499                 val = 133332000;
 500                 break;
 501         case 7:
 502                 val = 166665000;
 503                 break;
 504         }
 505
 506         return val;
 507 }