2 * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
10 #include <asm/immap_86xx.h>
11 #include <asm/fsl_pci.h>
12 #include <fsl_ddr_sdram.h>
13 #include <asm/fsl_serdes.h>
16 #include <fdt_support.h>
19 DECLARE_GLOBAL_DATA_PTR
;
21 phys_size_t
fixed_sdram(void);
26 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
28 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
29 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
30 in_8(pixis_base
+ PIXIS_ID
), in_8(pixis_base
+ PIXIS_VER
),
31 in_8(pixis_base
+ PIXIS_PVER
));
33 vboot
= in_8(pixis_base
+ PIXIS_VBOOT
);
34 if (vboot
& PIXIS_VBOOT_FMAP
)
35 printf ("vBank: %d\n", ((vboot
& PIXIS_VBOOT_FBANK
) >> 6));
44 phys_size_t dram_size
= 0;
46 #if defined(CONFIG_SPD_EEPROM)
47 dram_size
= fsl_ddr_sdram();
49 dram_size
= fixed_sdram();
52 setup_ddr_bat(dram_size
);
55 gd
->ram_size
= dram_size
;
61 #if !defined(CONFIG_SPD_EEPROM)
63 * Fixed sdram init -- doesn't use serial presence detect.
68 #if !defined(CONFIG_SYS_RAMBOOT)
69 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
70 struct ccsr_ddr __iomem
*ddr
= &immap
->im_ddr1
;
72 ddr
->cs0_bnds
= CONFIG_SYS_DDR_CS0_BNDS
;
73 ddr
->cs0_config
= CONFIG_SYS_DDR_CS0_CONFIG
;
74 ddr
->timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
75 ddr
->timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
76 ddr
->timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
77 ddr
->timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
78 ddr
->sdram_mode
= CONFIG_SYS_DDR_MODE_1
;
79 ddr
->sdram_mode_2
= CONFIG_SYS_DDR_MODE_2
;
80 ddr
->sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
81 ddr
->sdram_data_init
= CONFIG_SYS_DDR_DATA_INIT
;
82 ddr
->sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL
;
83 ddr
->sdram_ocd_cntl
= CONFIG_SYS_DDR_OCD_CTRL
;
84 ddr
->sdram_ocd_status
= CONFIG_SYS_DDR_OCD_STATUS
;
86 #if defined (CONFIG_DDR_ECC)
87 ddr
->err_disable
= 0x0000008D;
88 ddr
->err_sbe
= 0x00ff0000;
94 #if defined (CONFIG_DDR_ECC)
95 /* Enable ECC checking */
96 ddr
->sdram_cfg
= (CONFIG_SYS_DDR_CONTROL
| 0x20000000);
98 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CONTROL
;
99 ddr
->sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL2
;
105 return CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
107 #endif /* !defined(CONFIG_SPD_EEPROM) */
109 void pci_init_board(void)
111 fsl_pcie_init_board(0);
115 * Activate ULI1575 legacy chip by performing a fake
116 * memory access. Needed to make ULI RTC work.
118 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
119 + CONFIG_SYS_PCIE1_MEM_SIZE
- 0x1000000)));
120 #endif /* CONFIG_PCIE1 */
124 #if defined(CONFIG_OF_BOARD_SETUP)
125 int ft_board_setup(void *blob
, bd_t
*bd
)
131 ft_cpu_setup(blob
, bd
);
136 * Warn if it looks like the device tree doesn't match u-boot.
137 * This is just an estimation, based on the location of CCSR,
138 * which is defined by the "reg" property in the soc node.
140 off
= fdt_path_offset(blob
, "/soc8641");
141 addrcells
= fdt_address_cells(blob
, 0);
142 tmp
= (u64
*)fdt_getprop(blob
, off
, "reg", NULL
);
152 if (addr
!= CONFIG_SYS_CCSRBAR_PHYS
)
153 printf("WARNING: The CCSRBAR address in your .dts "
154 "does not match the address of the CCSR "
155 "in u-boot. This means your .dts might "
166 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
170 get_board_sys_clk(ulong dummy
)
172 u8 i
, go_bit
, rd_clks
;
174 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
176 go_bit
= in_8(pixis_base
+ PIXIS_VCTL
);
179 rd_clks
= in_8(pixis_base
+ PIXIS_VCFGEN0
);
183 * Only if both go bit and the SCLK bit in VCFGEN0 are set
184 * should we be using the AUX register. Remember, we also set the
185 * GO bit to boot from the alternate bank on the on-board flash
190 i
= in_8(pixis_base
+ PIXIS_AUX
);
192 i
= in_8(pixis_base
+ PIXIS_SPD
);
194 i
= in_8(pixis_base
+ PIXIS_SPD
);
229 int board_eth_init(bd_t
*bis
)
231 /* Initialize TSECs */
233 return pci_eth_init(bis
);
236 void board_reset(void)
238 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
240 out_8(pixis_base
+ PIXIS_RST
, 0);