board/freescale/mpc8641hpcn/mpc8641hpcn.c

   1 /*
   2  * Copyright 2006, 2007 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <pci.h>
  25 #include <asm/processor.h>
  26 #include <asm/immap_86xx.h>
  27 #include <asm/fsl_pci.h>
  28 #include <asm/fsl_ddr_sdram.h>
  29 #include <asm/io.h>
  30 #include <libfdt.h>
  31 #include <fdt_support.h>
  32 #include <netdev.h>
  33
  34 #include "../common/pixis.h"
  35
  36 phys_size_t fixed_sdram(void);
  37
  38 int board_early_init_f(void)
  39 {
  40         return 0;
  41 }
  42
  43 int checkboard(void)
  44 {
  45         printf ("Board: MPC8641HPCN, System ID: 0x%02x, "
  46                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  47                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  48                 in8(PIXIS_BASE + PIXIS_PVER));
  49 #ifdef CONFIG_PHYS_64BIT
  50         printf ("       36-bit physical address map\n");
  51 #endif
  52         return 0;
  53 }
  54
  55
  56 phys_size_t
  57 initdram(int board_type)
  58 {
  59         phys_size_t dram_size = 0;
  60
  61 #if defined(CONFIG_SPD_EEPROM)
  62         dram_size = fsl_ddr_sdram();
  63 #else
  64         dram_size = fixed_sdram();
  65 #endif
  66
  67 #if defined(CONFIG_SYS_RAMBOOT)
  68         puts("    DDR: ");
  69         return dram_size;
  70 #endif
  71
  72         puts("    DDR: ");
  73         return dram_size;
  74 }
  75
  76
  77 #if !defined(CONFIG_SPD_EEPROM)
  78 /*
  79  * Fixed sdram init -- doesn't use serial presence detect.
  80  */
  81 phys_size_t
  82 fixed_sdram(void)
  83 {
  84 #if !defined(CONFIG_SYS_RAMBOOT)
  85         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  86         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
  87
  88         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  89         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  90         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  91         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  92         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  93         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  94         ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
  95         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  96         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  97         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  98         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  99         ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
 100         ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
 101
 102 #if defined (CONFIG_DDR_ECC)
 103         ddr->err_disable = 0x0000008D;
 104         ddr->err_sbe = 0x00ff0000;
 105 #endif
 106         asm("sync;isync");
 107
 108         udelay(500);
 109
 110 #if defined (CONFIG_DDR_ECC)
 111         /* Enable ECC checking */
 112         ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 113 #else
 114         ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
 115         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 116 #endif
 117         asm("sync; isync");
 118
 119         udelay(500);
 120 #endif
 121         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 122 }
 123 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 124
 125
 126 #if defined(CONFIG_PCI)
 127 static struct pci_controller pci1_hose;
 128 #endif /* CONFIG_PCI */
 129
 130 #ifdef CONFIG_PCI2
 131 static struct pci_controller pci2_hose;
 132 #endif  /* CONFIG_PCI2 */
 133
 134 int first_free_busno = 0;
 135
 136 void pci_init_board(void)
 137 {
 138 #ifdef CONFIG_PCI1
 139 {
 140         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 141         struct pci_controller *hose = &pci1_hose;
 142         struct pci_region *r = hose->regions;
 143         volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 144         volatile ccsr_gur_t *gur = &immap->im_gur;
 145         uint devdisr = gur->devdisr;
 146         uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 147                 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 148
 149 #ifdef DEBUG
 150         uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
 151                 >> MPC8641_PORBMSR_HA_SHIFT;
 152         uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 153 #endif
 154         if ((io_sel == 2 || io_sel == 3 || io_sel == 5
 155              || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
 156             && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
 157                 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
 158                 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
 159                 if (pci->pme_msg_det) {
 160                         pci->pme_msg_det = 0xffffffff;
 161                         debug(" with errors.  Clearing.  Now 0x%08x",
 162                               pci->pme_msg_det);
 163                 }
 164                 debug("\n");
 165
 166                 /* outbound memory */
 167                 pci_set_region(r++,
 168                                CONFIG_SYS_PCI1_MEM_BUS,
 169                                CONFIG_SYS_PCI1_MEM_PHYS,
 170                                CONFIG_SYS_PCI1_MEM_SIZE,
 171                                PCI_REGION_MEM);
 172
 173                 /* outbound io */
 174                 pci_set_region(r++,
 175                                CONFIG_SYS_PCI1_IO_BUS,
 176                                CONFIG_SYS_PCI1_IO_PHYS,
 177                                CONFIG_SYS_PCI1_IO_SIZE,
 178                                PCI_REGION_IO);
 179
 180                 /* inbound */
 181                 r += fsl_pci_setup_inbound_windows(r);
 182
 183                 hose->region_count = r - hose->regions;
 184
 185                 hose->first_busno=first_free_busno;
 186                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 187
 188                 fsl_pci_init(hose);
 189
 190                 first_free_busno=hose->last_busno+1;
 191                 printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
 192                         hose->first_busno,hose->last_busno);
 193
 194                 /*
 195                  * Activate ULI1575 legacy chip by performing a fake
 196                  * memory access.  Needed to make ULI RTC work.
 197                  */
 198                 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT
 199                                        + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
 200
 201         } else {
 202                 puts("PCI-EXPRESS 1: Disabled\n");
 203         }
 204 }
 205 #else
 206         puts("PCI-EXPRESS1: Disabled\n");
 207 #endif /* CONFIG_PCI1 */
 208
 209 #ifdef CONFIG_PCI2
 210 {
 211         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
 212         struct pci_controller *hose = &pci2_hose;
 213         struct pci_region *r = hose->regions;
 214
 215         /* outbound memory */
 216         pci_set_region(r++,
 217                        CONFIG_SYS_PCI2_MEM_BUS,
 218                        CONFIG_SYS_PCI2_MEM_PHYS,
 219                        CONFIG_SYS_PCI2_MEM_SIZE,
 220                        PCI_REGION_MEM);
 221
 222         /* outbound io */
 223         pci_set_region(r++,
 224                        CONFIG_SYS_PCI2_IO_BUS,
 225                        CONFIG_SYS_PCI2_IO_PHYS,
 226                        CONFIG_SYS_PCI2_IO_SIZE,
 227                        PCI_REGION_IO);
 228
 229         /* inbound */
 230         r += fsl_pci_setup_inbound_windows(r);
 231
 232         hose->region_count = r - hose->regions;
 233
 234         hose->first_busno=first_free_busno;
 235         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 236
 237         fsl_pci_init(hose);
 238
 239         first_free_busno=hose->last_busno+1;
 240         printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
 241                 hose->first_busno,hose->last_busno);
 242 }
 243 #else
 244         puts("PCI-EXPRESS 2: Disabled\n");
 245 #endif /* CONFIG_PCI2 */
 246
 247 }
 248
 249
 250 #if defined(CONFIG_OF_BOARD_SETUP)
 251 void
 252 ft_board_setup(void *blob, bd_t *bd)
 253 {
 254         int off;
 255         u64 *tmp;
 256         u32 *addrcells;
 257
 258         ft_cpu_setup(blob, bd);
 259
 260 #ifdef CONFIG_PCI1
 261         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 262 #endif
 263 #ifdef CONFIG_PCI2
 264         ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
 265 #endif
 266
 267         /*
 268          * Warn if it looks like the device tree doesn't match u-boot.
 269          * This is just an estimation, based on the location of CCSR,
 270          * which is defined by the "reg" property in the soc node.
 271          */
 272         off = fdt_path_offset(blob, "/soc8641");
 273         addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
 274         tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
 275
 276         if (tmp) {
 277                 u64 addr;
 278                 if (addrcells && (*addrcells == 1))
 279                         addr = *(u32 *)tmp;
 280                 else
 281                         addr = *tmp;
 282
 283                 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
 284                         printf("WARNING: The CCSRBAR address in your .dts "
 285                                "does not match the address of the CCSR "
 286                                "in u-boot.  This means your .dts might "
 287                                "be old.\n");
 288         }
 289 }
 290 #endif
 291
 292
 293 /*
 294  * get_board_sys_clk
 295  *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 296  */
 297
 298 unsigned long
 299 get_board_sys_clk(ulong dummy)
 300 {
 301         u8 i, go_bit, rd_clks;
 302         ulong val = 0;
 303
 304         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 305         go_bit &= 0x01;
 306
 307         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 308         rd_clks &= 0x1C;
 309
 310         /*
 311          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 312          * should we be using the AUX register. Remember, we also set the
 313          * GO bit to boot from the alternate bank on the on-board flash
 314          */
 315
 316         if (go_bit) {
 317                 if (rd_clks == 0x1c)
 318                         i = in8(PIXIS_BASE + PIXIS_AUX);
 319                 else
 320                         i = in8(PIXIS_BASE + PIXIS_SPD);
 321         } else {
 322                 i = in8(PIXIS_BASE + PIXIS_SPD);
 323         }
 324
 325         i &= 0x07;
 326
 327         switch (i) {
 328         case 0:
 329                 val = 33000000;
 330                 break;
 331         case 1:
 332                 val = 40000000;
 333                 break;
 334         case 2:
 335                 val = 50000000;
 336                 break;
 337         case 3:
 338                 val = 66000000;
 339                 break;
 340         case 4:
 341                 val = 83000000;
 342                 break;
 343         case 5:
 344                 val = 100000000;
 345                 break;
 346         case 6:
 347                 val = 134000000;
 348                 break;
 349         case 7:
 350                 val = 166000000;
 351                 break;
 352         }
 353
 354         return val;
 355 }
 356
 357 int board_eth_init(bd_t *bis)
 358 {
 359         /* Initialize TSECs */
 360         cpu_eth_init(bis);
 361         return pci_eth_init(bis);
 362 }
 363
 364 void board_reset(void)
 365 {
 366         out8(PIXIS_BASE + PIXIS_RST, 0);
 367
 368         while (1)
 369                 ;
 370 }
 371
 372 #ifdef CONFIG_MP
 373 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 374
 375 void board_lmb_reserve(struct lmb *lmb)
 376 {
 377         cpu_mp_lmb_reserve(lmb);
 378 }
 379 #endif