board/freescale/mpc8641hpcn/mpc8641hpcn.c

   1 /*
   2  * Copyright 2006, 2007 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <pci.h>
  25 #include <asm/processor.h>
  26 #include <asm/immap_86xx.h>
  27 #include <asm/immap_fsl_pci.h>
  28 #include <spd_sdram.h>
  29 #include <asm/io.h>
  30 #include <libfdt.h>
  31 #include <fdt_support.h>
  32
  33 #include "../common/pixis.h"
  34
  35 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  36 extern void ddr_enable_ecc(unsigned int dram_size);
  37 #endif
  38
  39 void sdram_init(void);
  40 long int fixed_sdram(void);
  41
  42
  43 int board_early_init_f(void)
  44 {
  45         return 0;
  46 }
  47
  48 int checkboard(void)
  49 {
  50         puts("Board: MPC8641HPCN\n");
  51
  52         return 0;
  53 }
  54
  55
  56 long int
  57 initdram(int board_type)
  58 {
  59         long dram_size = 0;
  60
  61 #if defined(CONFIG_SPD_EEPROM)
  62         dram_size = spd_sdram();
  63 #else
  64         dram_size = fixed_sdram();
  65 #endif
  66
  67 #if defined(CFG_RAMBOOT)
  68         puts("    DDR: ");
  69         return dram_size;
  70 #endif
  71
  72 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  73         /*
  74          * Initialize and enable DDR ECC.
  75          */
  76         ddr_enable_ecc(dram_size);
  77 #endif
  78
  79         puts("    DDR: ");
  80         return dram_size;
  81 }
  82
  83
  84 #if defined(CFG_DRAM_TEST)
  85 int
  86 testdram(void)
  87 {
  88         uint *pstart = (uint *) CFG_MEMTEST_START;
  89         uint *pend = (uint *) CFG_MEMTEST_END;
  90         uint *p;
  91
  92         puts("SDRAM test phase 1:\n");
  93         for (p = pstart; p < pend; p++)
  94                 *p = 0xaaaaaaaa;
  95
  96         for (p = pstart; p < pend; p++) {
  97                 if (*p != 0xaaaaaaaa) {
  98                         printf("SDRAM test fails at: %08x\n", (uint) p);
  99                         return 1;
 100                 }
 101         }
 102
 103         puts("SDRAM test phase 2:\n");
 104         for (p = pstart; p < pend; p++)
 105                 *p = 0x55555555;
 106
 107         for (p = pstart; p < pend; p++) {
 108                 if (*p != 0x55555555) {
 109                         printf("SDRAM test fails at: %08x\n", (uint) p);
 110                         return 1;
 111                 }
 112         }
 113
 114         puts("SDRAM test passed.\n");
 115         return 0;
 116 }
 117 #endif
 118
 119
 120 #if !defined(CONFIG_SPD_EEPROM)
 121 /*
 122  * Fixed sdram init -- doesn't use serial presence detect.
 123  */
 124 long int
 125 fixed_sdram(void)
 126 {
 127 #if !defined(CFG_RAMBOOT)
 128         volatile immap_t *immap = (immap_t *) CFG_IMMR;
 129         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 130
 131         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
 132         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
 133         ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
 134         ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
 135         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 136         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
 137         ddr->sdram_mode_1 = CFG_DDR_MODE_1;
 138         ddr->sdram_mode_2 = CFG_DDR_MODE_2;
 139         ddr->sdram_interval = CFG_DDR_INTERVAL;
 140         ddr->sdram_data_init = CFG_DDR_DATA_INIT;
 141         ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
 142         ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
 143         ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
 144
 145 #if defined (CONFIG_DDR_ECC)
 146         ddr->err_disable = 0x0000008D;
 147         ddr->err_sbe = 0x00ff0000;
 148 #endif
 149         asm("sync;isync");
 150
 151         udelay(500);
 152
 153 #if defined (CONFIG_DDR_ECC)
 154         /* Enable ECC checking */
 155         ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
 156 #else
 157         ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
 158         ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
 159 #endif
 160         asm("sync; isync");
 161
 162         udelay(500);
 163 #endif
 164         return CFG_SDRAM_SIZE * 1024 * 1024;
 165 }
 166 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 167
 168
 169 #if defined(CONFIG_PCI)
 170 /*
 171  * Initialize PCI Devices, report devices found.
 172  */
 173
 174 #ifndef CONFIG_PCI_PNP
 175 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 176         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 177          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 178          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 179                                      PCI_ENET0_MEMADDR,
 180                                      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
 181         {}
 182 };
 183 #endif
 184
 185
 186 static struct pci_controller pci1_hose = {
 187 #ifndef CONFIG_PCI_PNP
 188         config_table:pci_mpc86xxcts_config_table
 189 #endif
 190 };
 191 #endif /* CONFIG_PCI */
 192
 193 #ifdef CONFIG_PCI2
 194 static struct pci_controller pci2_hose;
 195 #endif  /* CONFIG_PCI2 */
 196
 197 int first_free_busno = 0;
 198
 199
 200 void pci_init_board(void)
 201 {
 202         volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 203         volatile ccsr_gur_t *gur = &immap->im_gur;
 204         uint devdisr = gur->devdisr;
 205         uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 206                 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 207
 208 #ifdef CONFIG_PCI1
 209 {
 210         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 211         extern void fsl_pci_init(struct pci_controller *hose);
 212         struct pci_controller *hose = &pci1_hose;
 213 #ifdef DEBUG
 214         uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
 215                 >> MPC8641_PORBMSR_HA_SHIFT;
 216         uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 217 #endif
 218         if ((io_sel == 2 || io_sel == 3 || io_sel == 5
 219              || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
 220             && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
 221                 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
 222                 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
 223                 if (pci->pme_msg_det) {
 224                         pci->pme_msg_det = 0xffffffff;
 225                         debug(" with errors.  Clearing.  Now 0x%08x",
 226                               pci->pme_msg_det);
 227                 }
 228                 debug("\n");
 229
 230                 /* inbound */
 231                 pci_set_region(hose->regions + 0,
 232                                CFG_PCI_MEMORY_BUS,
 233                                CFG_PCI_MEMORY_PHYS,
 234                                CFG_PCI_MEMORY_SIZE,
 235                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 236
 237                 /* outbound memory */
 238                 pci_set_region(hose->regions + 1,
 239                                CFG_PCI1_MEM_BASE,
 240                                CFG_PCI1_MEM_PHYS,
 241                                CFG_PCI1_MEM_SIZE,
 242                                PCI_REGION_MEM);
 243
 244                 /* outbound io */
 245                 pci_set_region(hose->regions + 2,
 246                                CFG_PCI1_IO_BASE,
 247                                CFG_PCI1_IO_PHYS,
 248                                CFG_PCI1_IO_SIZE,
 249                                PCI_REGION_IO);
 250
 251                 hose->region_count = 3;
 252
 253                 hose->first_busno=first_free_busno;
 254                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 255
 256                 fsl_pci_init(hose);
 257
 258                 first_free_busno=hose->last_busno+1;
 259                 printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
 260                         hose->first_busno,hose->last_busno);
 261
 262                 /*
 263                  * Activate ULI1575 legacy chip by performing a fake
 264                  * memory access.  Needed to make ULI RTC work.
 265                  */
 266                 in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
 267                                        + CFG_PCI1_MEM_SIZE - 0x1000000)));
 268
 269         } else {
 270                 puts("PCI-EXPRESS 1: Disabled\n");
 271         }
 272 }
 273 #else
 274         puts("PCI-EXPRESS1: Disabled\n");
 275 #endif /* CONFIG_PCI1 */
 276
 277 #ifdef CONFIG_PCI2
 278 {
 279         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
 280         extern void fsl_pci_init(struct pci_controller *hose);
 281         struct pci_controller *hose = &pci2_hose;
 282
 283
 284         /* inbound */
 285         pci_set_region(hose->regions + 0,
 286                        CFG_PCI_MEMORY_BUS,
 287                        CFG_PCI_MEMORY_PHYS,
 288                        CFG_PCI_MEMORY_SIZE,
 289                        PCI_REGION_MEM | PCI_REGION_MEMORY);
 290
 291         /* outbound memory */
 292         pci_set_region(hose->regions + 1,
 293                        CFG_PCI2_MEM_BASE,
 294                        CFG_PCI2_MEM_PHYS,
 295                        CFG_PCI2_MEM_SIZE,
 296                        PCI_REGION_MEM);
 297
 298         /* outbound io */
 299         pci_set_region(hose->regions + 2,
 300                        CFG_PCI2_IO_BASE,
 301                        CFG_PCI2_IO_PHYS,
 302                        CFG_PCI2_IO_SIZE,
 303                        PCI_REGION_IO);
 304
 305         hose->region_count = 3;
 306
 307         hose->first_busno=first_free_busno;
 308         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 309
 310         fsl_pci_init(hose);
 311
 312         first_free_busno=hose->last_busno+1;
 313         printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
 314                 hose->first_busno,hose->last_busno);
 315 }
 316 #else
 317         puts("PCI-EXPRESS 2: Disabled\n");
 318 #endif /* CONFIG_PCI2 */
 319
 320 }
 321
 322
 323 #if defined(CONFIG_OF_BOARD_SETUP)
 324
 325 void
 326 ft_board_setup(void *blob, bd_t *bd)
 327 {
 328         int node, tmp[2];
 329         const char *path;
 330
 331         ft_cpu_setup(blob, bd);
 332
 333         node = fdt_path_offset(blob, "/aliases");
 334         tmp[0] = 0;
 335         if (node >= 0) {
 336 #ifdef CONFIG_PCI1
 337                 path = fdt_getprop(blob, node, "pci0", NULL);
 338                 if (path) {
 339                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 340                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 341                 }
 342 #endif
 343 #ifdef CONFIG_PCI2
 344                 path = fdt_getprop(blob, node, "pci1", NULL);
 345                 if (path) {
 346                         tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
 347                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 348                 }
 349 #endif
 350         }
 351 }
 352 #endif
 353
 354
 355 /*
 356  * get_board_sys_clk
 357  *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 358  */
 359
 360 unsigned long
 361 get_board_sys_clk(ulong dummy)
 362 {
 363         u8 i, go_bit, rd_clks;
 364         ulong val = 0;
 365
 366         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 367         go_bit &= 0x01;
 368
 369         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 370         rd_clks &= 0x1C;
 371
 372         /*
 373          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 374          * should we be using the AUX register. Remember, we also set the
 375          * GO bit to boot from the alternate bank on the on-board flash
 376          */
 377
 378         if (go_bit) {
 379                 if (rd_clks == 0x1c)
 380                         i = in8(PIXIS_BASE + PIXIS_AUX);
 381                 else
 382                         i = in8(PIXIS_BASE + PIXIS_SPD);
 383         } else {
 384                 i = in8(PIXIS_BASE + PIXIS_SPD);
 385         }
 386
 387         i &= 0x07;
 388
 389         switch (i) {
 390         case 0:
 391                 val = 33000000;
 392                 break;
 393         case 1:
 394                 val = 40000000;
 395                 break;
 396         case 2:
 397                 val = 50000000;
 398                 break;
 399         case 3:
 400                 val = 66000000;
 401                 break;
 402         case 4:
 403                 val = 83000000;
 404                 break;
 405         case 5:
 406                 val = 100000000;
 407                 break;
 408         case 6:
 409                 val = 134000000;
 410                 break;
 411         case 7:
 412                 val = 166000000;
 413                 break;
 414         }
 415
 416         return val;
 417 }