board/freescale/mpc8641hpcn/mpc8641hpcn.c

   1 /*
   2  * Copyright 2006, 2007 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <pci.h>
  25 #include <asm/processor.h>
  26 #include <asm/immap_86xx.h>
  27 #include <asm/immap_fsl_pci.h>
  28 #include <spd_sdram.h>
  29 #include <asm/io.h>
  30 #include <libfdt.h>
  31 #include <fdt_support.h>
  32
  33 #include "../common/pixis.h"
  34
  35 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  36 extern void ddr_enable_ecc(unsigned int dram_size);
  37 #endif
  38
  39 void sdram_init(void);
  40 long int fixed_sdram(void);
  41
  42
  43 int board_early_init_f(void)
  44 {
  45         return 0;
  46 }
  47
  48 int checkboard(void)
  49 {
  50         puts("Board: MPC8641HPCN\n");
  51
  52         return 0;
  53 }
  54
  55
  56 long int
  57 initdram(int board_type)
  58 {
  59         long dram_size = 0;
  60
  61 #if defined(CONFIG_SPD_EEPROM)
  62         dram_size = spd_sdram();
  63 #else
  64         dram_size = fixed_sdram();
  65 #endif
  66
  67 #if defined(CFG_RAMBOOT)
  68         puts("    DDR: ");
  69         return dram_size;
  70 #endif
  71
  72 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  73         /*
  74          * Initialize and enable DDR ECC.
  75          */
  76         ddr_enable_ecc(dram_size);
  77 #endif
  78
  79         puts("    DDR: ");
  80         return dram_size;
  81 }
  82
  83
  84 #if !defined(CONFIG_SPD_EEPROM)
  85 /*
  86  * Fixed sdram init -- doesn't use serial presence detect.
  87  */
  88 long int
  89 fixed_sdram(void)
  90 {
  91 #if !defined(CFG_RAMBOOT)
  92         volatile immap_t *immap = (immap_t *) CFG_IMMR;
  93         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
  94
  95         ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
  96         ddr->cs0_config = CFG_DDR_CS0_CONFIG;
  97         ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
  98         ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
  99         ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
 100         ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
 101         ddr->sdram_mode_1 = CFG_DDR_MODE_1;
 102         ddr->sdram_mode_2 = CFG_DDR_MODE_2;
 103         ddr->sdram_interval = CFG_DDR_INTERVAL;
 104         ddr->sdram_data_init = CFG_DDR_DATA_INIT;
 105         ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
 106         ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
 107         ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
 108
 109 #if defined (CONFIG_DDR_ECC)
 110         ddr->err_disable = 0x0000008D;
 111         ddr->err_sbe = 0x00ff0000;
 112 #endif
 113         asm("sync;isync");
 114
 115         udelay(500);
 116
 117 #if defined (CONFIG_DDR_ECC)
 118         /* Enable ECC checking */
 119         ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
 120 #else
 121         ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
 122         ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
 123 #endif
 124         asm("sync; isync");
 125
 126         udelay(500);
 127 #endif
 128         return CFG_SDRAM_SIZE * 1024 * 1024;
 129 }
 130 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 131
 132
 133 #if defined(CONFIG_PCI)
 134 /*
 135  * Initialize PCI Devices, report devices found.
 136  */
 137
 138 #ifndef CONFIG_PCI_PNP
 139 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 140         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 141          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 142          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 143                                      PCI_ENET0_MEMADDR,
 144                                      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
 145         {}
 146 };
 147 #endif
 148
 149
 150 static struct pci_controller pci1_hose = {
 151 #ifndef CONFIG_PCI_PNP
 152         config_table:pci_mpc86xxcts_config_table
 153 #endif
 154 };
 155 #endif /* CONFIG_PCI */
 156
 157 #ifdef CONFIG_PCI2
 158 static struct pci_controller pci2_hose;
 159 #endif  /* CONFIG_PCI2 */
 160
 161 int first_free_busno = 0;
 162
 163
 164 void pci_init_board(void)
 165 {
 166         volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 167         volatile ccsr_gur_t *gur = &immap->im_gur;
 168         uint devdisr = gur->devdisr;
 169         uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 170                 >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 171
 172 #ifdef CONFIG_PCI1
 173 {
 174         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 175         extern void fsl_pci_init(struct pci_controller *hose);
 176         struct pci_controller *hose = &pci1_hose;
 177 #ifdef DEBUG
 178         uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
 179                 >> MPC8641_PORBMSR_HA_SHIFT;
 180         uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
 181 #endif
 182         if ((io_sel == 2 || io_sel == 3 || io_sel == 5
 183              || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
 184             && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
 185                 debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
 186                 debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
 187                 if (pci->pme_msg_det) {
 188                         pci->pme_msg_det = 0xffffffff;
 189                         debug(" with errors.  Clearing.  Now 0x%08x",
 190                               pci->pme_msg_det);
 191                 }
 192                 debug("\n");
 193
 194                 /* inbound */
 195                 pci_set_region(hose->regions + 0,
 196                                CFG_PCI_MEMORY_BUS,
 197                                CFG_PCI_MEMORY_PHYS,
 198                                CFG_PCI_MEMORY_SIZE,
 199                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 200
 201                 /* outbound memory */
 202                 pci_set_region(hose->regions + 1,
 203                                CFG_PCI1_MEM_BASE,
 204                                CFG_PCI1_MEM_PHYS,
 205                                CFG_PCI1_MEM_SIZE,
 206                                PCI_REGION_MEM);
 207
 208                 /* outbound io */
 209                 pci_set_region(hose->regions + 2,
 210                                CFG_PCI1_IO_BASE,
 211                                CFG_PCI1_IO_PHYS,
 212                                CFG_PCI1_IO_SIZE,
 213                                PCI_REGION_IO);
 214
 215                 hose->region_count = 3;
 216
 217                 hose->first_busno=first_free_busno;
 218                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 219
 220                 fsl_pci_init(hose);
 221
 222                 first_free_busno=hose->last_busno+1;
 223                 printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
 224                         hose->first_busno,hose->last_busno);
 225
 226                 /*
 227                  * Activate ULI1575 legacy chip by performing a fake
 228                  * memory access.  Needed to make ULI RTC work.
 229                  */
 230                 in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
 231                                        + CFG_PCI1_MEM_SIZE - 0x1000000)));
 232
 233         } else {
 234                 puts("PCI-EXPRESS 1: Disabled\n");
 235         }
 236 }
 237 #else
 238         puts("PCI-EXPRESS1: Disabled\n");
 239 #endif /* CONFIG_PCI1 */
 240
 241 #ifdef CONFIG_PCI2
 242 {
 243         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
 244         extern void fsl_pci_init(struct pci_controller *hose);
 245         struct pci_controller *hose = &pci2_hose;
 246
 247
 248         /* inbound */
 249         pci_set_region(hose->regions + 0,
 250                        CFG_PCI_MEMORY_BUS,
 251                        CFG_PCI_MEMORY_PHYS,
 252                        CFG_PCI_MEMORY_SIZE,
 253                        PCI_REGION_MEM | PCI_REGION_MEMORY);
 254
 255         /* outbound memory */
 256         pci_set_region(hose->regions + 1,
 257                        CFG_PCI2_MEM_BASE,
 258                        CFG_PCI2_MEM_PHYS,
 259                        CFG_PCI2_MEM_SIZE,
 260                        PCI_REGION_MEM);
 261
 262         /* outbound io */
 263         pci_set_region(hose->regions + 2,
 264                        CFG_PCI2_IO_BASE,
 265                        CFG_PCI2_IO_PHYS,
 266                        CFG_PCI2_IO_SIZE,
 267                        PCI_REGION_IO);
 268
 269         hose->region_count = 3;
 270
 271         hose->first_busno=first_free_busno;
 272         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 273
 274         fsl_pci_init(hose);
 275
 276         first_free_busno=hose->last_busno+1;
 277         printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
 278                 hose->first_busno,hose->last_busno);
 279 }
 280 #else
 281         puts("PCI-EXPRESS 2: Disabled\n");
 282 #endif /* CONFIG_PCI2 */
 283
 284 }
 285
 286
 287 #if defined(CONFIG_OF_BOARD_SETUP)
 288
 289 void
 290 ft_board_setup(void *blob, bd_t *bd)
 291 {
 292         int node, tmp[2];
 293         const char *path;
 294
 295         ft_cpu_setup(blob, bd);
 296
 297         node = fdt_path_offset(blob, "/aliases");
 298         tmp[0] = 0;
 299         if (node >= 0) {
 300 #ifdef CONFIG_PCI1
 301                 path = fdt_getprop(blob, node, "pci0", NULL);
 302                 if (path) {
 303                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 304                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 305                 }
 306 #endif
 307 #ifdef CONFIG_PCI2
 308                 path = fdt_getprop(blob, node, "pci1", NULL);
 309                 if (path) {
 310                         tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
 311                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 312                 }
 313 #endif
 314         }
 315 }
 316 #endif
 317
 318
 319 /*
 320  * get_board_sys_clk
 321  *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 322  */
 323
 324 unsigned long
 325 get_board_sys_clk(ulong dummy)
 326 {
 327         u8 i, go_bit, rd_clks;
 328         ulong val = 0;
 329
 330         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 331         go_bit &= 0x01;
 332
 333         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 334         rd_clks &= 0x1C;
 335
 336         /*
 337          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 338          * should we be using the AUX register. Remember, we also set the
 339          * GO bit to boot from the alternate bank on the on-board flash
 340          */
 341
 342         if (go_bit) {
 343                 if (rd_clks == 0x1c)
 344                         i = in8(PIXIS_BASE + PIXIS_AUX);
 345                 else
 346                         i = in8(PIXIS_BASE + PIXIS_SPD);
 347         } else {
 348                 i = in8(PIXIS_BASE + PIXIS_SPD);
 349         }
 350
 351         i &= 0x07;
 352
 353         switch (i) {
 354         case 0:
 355                 val = 33000000;
 356                 break;
 357         case 1:
 358                 val = 40000000;
 359                 break;
 360         case 2:
 361                 val = 50000000;
 362                 break;
 363         case 3:
 364                 val = 66000000;
 365                 break;
 366         case 4:
 367                 val = 83000000;
 368                 break;
 369         case 5:
 370                 val = 100000000;
 371                 break;
 372         case 6:
 373                 val = 134000000;
 374                 break;
 375         case 7:
 376                 val = 166000000;
 377                 break;
 378         }
 379
 380         return val;
 381 }