2 * Copyright 2006, 2007 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <asm/immap_86xx.h>
27 #include <asm/immap_fsl_pci.h>
31 #if defined(CONFIG_OF_FLAT_TREE)
33 extern void ft_cpu_setup(void *blob
, bd_t
*bd
);
36 #include "../common/pixis.h"
38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
39 extern void ddr_enable_ecc(unsigned int dram_size
);
42 #if defined(CONFIG_SPD_EEPROM)
43 #include "spd_sdram.h"
46 void sdram_init(void);
47 long int fixed_sdram(void);
50 int board_early_init_f(void)
57 puts("Board: MPC8641HPCN\n");
64 initdram(int board_type
)
68 #if defined(CONFIG_SPD_EEPROM)
69 dram_size
= spd_sdram();
71 dram_size
= fixed_sdram();
74 #if defined(CFG_RAMBOOT)
79 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
81 * Initialize and enable DDR ECC.
83 ddr_enable_ecc(dram_size
);
91 #if defined(CFG_DRAM_TEST)
95 uint
*pstart
= (uint
*) CFG_MEMTEST_START
;
96 uint
*pend
= (uint
*) CFG_MEMTEST_END
;
99 puts("SDRAM test phase 1:\n");
100 for (p
= pstart
; p
< pend
; p
++)
103 for (p
= pstart
; p
< pend
; p
++) {
104 if (*p
!= 0xaaaaaaaa) {
105 printf("SDRAM test fails at: %08x\n", (uint
) p
);
110 puts("SDRAM test phase 2:\n");
111 for (p
= pstart
; p
< pend
; p
++)
114 for (p
= pstart
; p
< pend
; p
++) {
115 if (*p
!= 0x55555555) {
116 printf("SDRAM test fails at: %08x\n", (uint
) p
);
121 puts("SDRAM test passed.\n");
127 #if !defined(CONFIG_SPD_EEPROM)
129 * Fixed sdram init -- doesn't use serial presence detect.
134 #if !defined(CFG_RAMBOOT)
135 volatile immap_t
*immap
= (immap_t
*) CFG_IMMR
;
136 volatile ccsr_ddr_t
*ddr
= &immap
->im_ddr1
;
138 ddr
->cs0_bnds
= CFG_DDR_CS0_BNDS
;
139 ddr
->cs0_config
= CFG_DDR_CS0_CONFIG
;
140 ddr
->ext_refrec
= CFG_DDR_EXT_REFRESH
;
141 ddr
->timing_cfg_0
= CFG_DDR_TIMING_0
;
142 ddr
->timing_cfg_1
= CFG_DDR_TIMING_1
;
143 ddr
->timing_cfg_2
= CFG_DDR_TIMING_2
;
144 ddr
->sdram_mode_1
= CFG_DDR_MODE_1
;
145 ddr
->sdram_mode_2
= CFG_DDR_MODE_2
;
146 ddr
->sdram_interval
= CFG_DDR_INTERVAL
;
147 ddr
->sdram_data_init
= CFG_DDR_DATA_INIT
;
148 ddr
->sdram_clk_cntl
= CFG_DDR_CLK_CTRL
;
149 ddr
->sdram_ocd_cntl
= CFG_DDR_OCD_CTRL
;
150 ddr
->sdram_ocd_status
= CFG_DDR_OCD_STATUS
;
152 #if defined (CONFIG_DDR_ECC)
153 ddr
->err_disable
= 0x0000008D;
154 ddr
->err_sbe
= 0x00ff0000;
160 #if defined (CONFIG_DDR_ECC)
161 /* Enable ECC checking */
162 ddr
->sdram_cfg_1
= (CFG_DDR_CONTROL
| 0x20000000);
164 ddr
->sdram_cfg_1
= CFG_DDR_CONTROL
;
165 ddr
->sdram_cfg_2
= CFG_DDR_CONTROL2
;
171 return CFG_SDRAM_SIZE
* 1024 * 1024;
173 #endif /* !defined(CONFIG_SPD_EEPROM) */
176 #if defined(CONFIG_PCI)
178 * Initialize PCI Devices, report devices found.
181 #ifndef CONFIG_PCI_PNP
182 static struct pci_config_table pci_fsl86xxads_config_table
[] = {
183 {PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
, PCI_ANY_ID
,
184 PCI_IDSEL_NUMBER
, PCI_ANY_ID
,
185 pci_cfgfunc_config_device
, {PCI_ENET0_IOADDR
,
187 PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
}},
193 static struct pci_controller pci1_hose
= {
194 #ifndef CONFIG_PCI_PNP
195 config_table
:pci_mpc86xxcts_config_table
198 #endif /* CONFIG_PCI */
201 static struct pci_controller pci2_hose
;
202 #endif /* CONFIG_PCI2 */
204 int first_free_busno
= 0;
207 void pci_init_board(void)
209 volatile immap_t
*immap
= (immap_t
*) CFG_CCSRBAR
;
210 volatile ccsr_gur_t
*gur
= &immap
->im_gur
;
211 uint devdisr
= gur
->devdisr
;
212 uint io_sel
= (gur
->pordevsr
& MPC86xx_PORDEVSR_IO_SEL
) >> 16;
216 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CFG_PCI1_ADDR
;
217 extern void fsl_pci_init(struct pci_controller
*hose
);
218 struct pci_controller
*hose
= &pci1_hose
;
220 uint host1_agent
= (gur
->porbmsr
& MPC86xx_PORBMSR_HA
) >> 17;
221 uint pex1_agent
= (host1_agent
== 0) || (host1_agent
== 1);
223 if ((io_sel
== 2 || io_sel
== 3 || io_sel
== 5
224 || io_sel
== 6 || io_sel
== 7 || io_sel
== 0xF)
225 && !(devdisr
& MPC86xx_DEVDISR_PCIEX1
)) {
226 debug("PCI-EXPRESS 1: %s \n", pex1_agent
? "Agent" : "Host");
227 debug("0x%08x=0x%08x ", &pci
->pme_msg_det
, pci
->pme_msg_det
);
228 if (pci
->pme_msg_det
) {
229 pci
->pme_msg_det
= 0xffffffff;
230 debug(" with errors. Clearing. Now 0x%08x",
236 pci_set_region(hose
->regions
+ 0,
240 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
242 /* outbound memory */
243 pci_set_region(hose
->regions
+ 1,
250 pci_set_region(hose
->regions
+ 2,
256 hose
->region_count
= 3;
258 hose
->first_busno
=first_free_busno
;
259 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
263 first_free_busno
=hose
->last_busno
+1;
264 printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
265 hose
->first_busno
,hose
->last_busno
);
268 * Activate ULI1575 legacy chip by performing a fake
269 * memory access. Needed to make ULI RTC work.
271 in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
272 + CFG_PCI1_MEM_SIZE
- 0x1000000)));
275 puts("PCI-EXPRESS 1: Disabled\n");
279 puts("PCI-EXPRESS1: Disabled\n");
280 #endif /* CONFIG_PCI1 */
284 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) CFG_PCI2_ADDR
;
285 extern void fsl_pci_init(struct pci_controller
*hose
);
286 struct pci_controller
*hose
= &pci2_hose
;
290 pci_set_region(hose
->regions
+ 0,
294 PCI_REGION_MEM
| PCI_REGION_MEMORY
);
296 /* outbound memory */
297 pci_set_region(hose
->regions
+ 1,
304 pci_set_region(hose
->regions
+ 2,
310 hose
->region_count
= 3;
312 hose
->first_busno
=first_free_busno
;
313 pci_setup_indirect(hose
, (int) &pci
->cfg_addr
, (int) &pci
->cfg_data
);
317 first_free_busno
=hose
->last_busno
+1;
318 printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
319 hose
->first_busno
,hose
->last_busno
);
322 puts("PCI-EXPRESS 2: Disabled\n");
323 #endif /* CONFIG_PCI2 */
327 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
329 ft_board_setup(void *blob
, bd_t
*bd
)
334 ft_cpu_setup(blob
, bd
);
336 p
= ft_get_prop(blob
, "/memory/reg", &len
);
338 *p
++ = cpu_to_be32(bd
->bi_memstart
);
339 *p
= cpu_to_be32(bd
->bi_memsize
);
347 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
351 get_board_sys_clk(ulong dummy
)
353 u8 i
, go_bit
, rd_clks
;
356 go_bit
= in8(PIXIS_BASE
+ PIXIS_VCTL
);
359 rd_clks
= in8(PIXIS_BASE
+ PIXIS_VCFGEN0
);
363 * Only if both go bit and the SCLK bit in VCFGEN0 are set
364 * should we be using the AUX register. Remember, we also set the
365 * GO bit to boot from the alternate bank on the on-board flash
370 i
= in8(PIXIS_BASE
+ PIXIS_AUX
);
372 i
= in8(PIXIS_BASE
+ PIXIS_SPD
);
374 i
= in8(PIXIS_BASE
+ PIXIS_SPD
);