board/freescale/mpc8641hpcn/mpc8641hpcn.c

   1 /*
   2  * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <pci.h>
  25 #include <asm/processor.h>
  26 #include <asm/immap_86xx.h>
  27 #include <asm/fsl_pci.h>
  28 #include <asm/fsl_ddr_sdram.h>
  29 #include <asm/fsl_serdes.h>
  30 #include <asm/io.h>
  31 #include <libfdt.h>
  32 #include <fdt_support.h>
  33 #include <netdev.h>
  34
  35 phys_size_t fixed_sdram(void);
  36
  37 int checkboard(void)
  38 {
  39         u8 vboot;
  40         u8 *pixis_base = (u8 *)PIXIS_BASE;
  41
  42         printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
  43                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  44                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  45                 in_8(pixis_base + PIXIS_PVER));
  46
  47         vboot = in_8(pixis_base + PIXIS_VBOOT);
  48         if (vboot & PIXIS_VBOOT_FMAP)
  49                 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
  50         else
  51                 puts ("Promjet\n");
  52
  53         return 0;
  54 }
  55
  56 phys_size_t
  57 initdram(int board_type)
  58 {
  59         phys_size_t dram_size = 0;
  60
  61 #if defined(CONFIG_SPD_EEPROM)
  62         dram_size = fsl_ddr_sdram();
  63 #else
  64         dram_size = fixed_sdram();
  65 #endif
  66
  67         setup_ddr_bat(dram_size);
  68
  69         debug("    DDR: ");
  70         return dram_size;
  71 }
  72
  73
  74 #if !defined(CONFIG_SPD_EEPROM)
  75 /*
  76  * Fixed sdram init -- doesn't use serial presence detect.
  77  */
  78 phys_size_t
  79 fixed_sdram(void)
  80 {
  81 #if !defined(CONFIG_SYS_RAMBOOT)
  82         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  83         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
  84
  85         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  86         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  87         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  88         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  89         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  90         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  91         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  92         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  93         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  94         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  95         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  96         ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
  97         ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
  98
  99 #if defined (CONFIG_DDR_ECC)
 100         ddr->err_disable = 0x0000008D;
 101         ddr->err_sbe = 0x00ff0000;
 102 #endif
 103         asm("sync;isync");
 104
 105         udelay(500);
 106
 107 #if defined (CONFIG_DDR_ECC)
 108         /* Enable ECC checking */
 109         ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 110 #else
 111         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 112         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 113 #endif
 114         asm("sync; isync");
 115
 116         udelay(500);
 117 #endif
 118         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 119 }
 120 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 121
 122 void pci_init_board(void)
 123 {
 124         fsl_pcie_init_board(0);
 125
 126 #ifdef CONFIG_PCIE1
 127                 /*
 128                  * Activate ULI1575 legacy chip by performing a fake
 129                  * memory access.  Needed to make ULI RTC work.
 130                  */
 131                 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
 132                                        + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
 133 #endif /* CONFIG_PCIE1 */
 134 }
 135
 136
 137 #if defined(CONFIG_OF_BOARD_SETUP)
 138 void
 139 ft_board_setup(void *blob, bd_t *bd)
 140 {
 141         int off;
 142         u64 *tmp;
 143         u32 *addrcells;
 144
 145         ft_cpu_setup(blob, bd);
 146
 147         FT_FSL_PCI_SETUP;
 148
 149         /*
 150          * Warn if it looks like the device tree doesn't match u-boot.
 151          * This is just an estimation, based on the location of CCSR,
 152          * which is defined by the "reg" property in the soc node.
 153          */
 154         off = fdt_path_offset(blob, "/soc8641");
 155         addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
 156         tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
 157
 158         if (tmp) {
 159                 u64 addr;
 160                 if (addrcells && (*addrcells == 1))
 161                         addr = *(u32 *)tmp;
 162                 else
 163                         addr = *tmp;
 164
 165                 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
 166                         printf("WARNING: The CCSRBAR address in your .dts "
 167                                "does not match the address of the CCSR "
 168                                "in u-boot.  This means your .dts might "
 169                                "be old.\n");
 170         }
 171 }
 172 #endif
 173
 174
 175 /*
 176  * get_board_sys_clk
 177  *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 178  */
 179
 180 unsigned long
 181 get_board_sys_clk(ulong dummy)
 182 {
 183         u8 i, go_bit, rd_clks;
 184         ulong val = 0;
 185         u8 *pixis_base = (u8 *)PIXIS_BASE;
 186
 187         go_bit = in_8(pixis_base + PIXIS_VCTL);
 188         go_bit &= 0x01;
 189
 190         rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
 191         rd_clks &= 0x1C;
 192
 193         /*
 194          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 195          * should we be using the AUX register. Remember, we also set the
 196          * GO bit to boot from the alternate bank on the on-board flash
 197          */
 198
 199         if (go_bit) {
 200                 if (rd_clks == 0x1c)
 201                         i = in_8(pixis_base + PIXIS_AUX);
 202                 else
 203                         i = in_8(pixis_base + PIXIS_SPD);
 204         } else {
 205                 i = in_8(pixis_base + PIXIS_SPD);
 206         }
 207
 208         i &= 0x07;
 209
 210         switch (i) {
 211         case 0:
 212                 val = 33000000;
 213                 break;
 214         case 1:
 215                 val = 40000000;
 216                 break;
 217         case 2:
 218                 val = 50000000;
 219                 break;
 220         case 3:
 221                 val = 66000000;
 222                 break;
 223         case 4:
 224                 val = 83000000;
 225                 break;
 226         case 5:
 227                 val = 100000000;
 228                 break;
 229         case 6:
 230                 val = 134000000;
 231                 break;
 232         case 7:
 233                 val = 166000000;
 234                 break;
 235         }
 236
 237         return val;
 238 }
 239
 240 int board_eth_init(bd_t *bis)
 241 {
 242         /* Initialize TSECs */
 243         cpu_eth_init(bis);
 244         return pci_eth_init(bis);
 245 }
 246
 247 void board_reset(void)
 248 {
 249         u8 *pixis_base = (u8 *)PIXIS_BASE;
 250
 251         out_8(pixis_base + PIXIS_RST, 0);
 252
 253         while (1)
 254                 ;
 255 }