2 * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
10 #include <asm/immap_86xx.h>
11 #include <asm/fsl_pci.h>
12 #include <asm/fsl_ddr_sdram.h>
13 #include <asm/fsl_serdes.h>
16 #include <fdt_support.h>
19 phys_size_t
fixed_sdram(void);
24 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
26 printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
27 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
28 in_8(pixis_base
+ PIXIS_ID
), in_8(pixis_base
+ PIXIS_VER
),
29 in_8(pixis_base
+ PIXIS_PVER
));
31 vboot
= in_8(pixis_base
+ PIXIS_VBOOT
);
32 if (vboot
& PIXIS_VBOOT_FMAP
)
33 printf ("vBank: %d\n", ((vboot
& PIXIS_VBOOT_FBANK
) >> 6));
41 initdram(int board_type
)
43 phys_size_t dram_size
= 0;
45 #if defined(CONFIG_SPD_EEPROM)
46 dram_size
= fsl_ddr_sdram();
48 dram_size
= fixed_sdram();
51 setup_ddr_bat(dram_size
);
58 #if !defined(CONFIG_SPD_EEPROM)
60 * Fixed sdram init -- doesn't use serial presence detect.
65 #if !defined(CONFIG_SYS_RAMBOOT)
66 volatile immap_t
*immap
= (immap_t
*) CONFIG_SYS_IMMR
;
67 volatile ccsr_ddr_t
*ddr
= &immap
->im_ddr1
;
69 ddr
->cs0_bnds
= CONFIG_SYS_DDR_CS0_BNDS
;
70 ddr
->cs0_config
= CONFIG_SYS_DDR_CS0_CONFIG
;
71 ddr
->timing_cfg_3
= CONFIG_SYS_DDR_TIMING_3
;
72 ddr
->timing_cfg_0
= CONFIG_SYS_DDR_TIMING_0
;
73 ddr
->timing_cfg_1
= CONFIG_SYS_DDR_TIMING_1
;
74 ddr
->timing_cfg_2
= CONFIG_SYS_DDR_TIMING_2
;
75 ddr
->sdram_mode
= CONFIG_SYS_DDR_MODE_1
;
76 ddr
->sdram_mode_2
= CONFIG_SYS_DDR_MODE_2
;
77 ddr
->sdram_interval
= CONFIG_SYS_DDR_INTERVAL
;
78 ddr
->sdram_data_init
= CONFIG_SYS_DDR_DATA_INIT
;
79 ddr
->sdram_clk_cntl
= CONFIG_SYS_DDR_CLK_CTRL
;
80 ddr
->sdram_ocd_cntl
= CONFIG_SYS_DDR_OCD_CTRL
;
81 ddr
->sdram_ocd_status
= CONFIG_SYS_DDR_OCD_STATUS
;
83 #if defined (CONFIG_DDR_ECC)
84 ddr
->err_disable
= 0x0000008D;
85 ddr
->err_sbe
= 0x00ff0000;
91 #if defined (CONFIG_DDR_ECC)
92 /* Enable ECC checking */
93 ddr
->sdram_cfg
= (CONFIG_SYS_DDR_CONTROL
| 0x20000000);
95 ddr
->sdram_cfg
= CONFIG_SYS_DDR_CONTROL
;
96 ddr
->sdram_cfg_2
= CONFIG_SYS_DDR_CONTROL2
;
102 return CONFIG_SYS_SDRAM_SIZE
* 1024 * 1024;
104 #endif /* !defined(CONFIG_SPD_EEPROM) */
106 void pci_init_board(void)
108 fsl_pcie_init_board(0);
112 * Activate ULI1575 legacy chip by performing a fake
113 * memory access. Needed to make ULI RTC work.
115 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
116 + CONFIG_SYS_PCIE1_MEM_SIZE
- 0x1000000)));
117 #endif /* CONFIG_PCIE1 */
121 #if defined(CONFIG_OF_BOARD_SETUP)
123 ft_board_setup(void *blob
, bd_t
*bd
)
129 ft_cpu_setup(blob
, bd
);
134 * Warn if it looks like the device tree doesn't match u-boot.
135 * This is just an estimation, based on the location of CCSR,
136 * which is defined by the "reg" property in the soc node.
138 off
= fdt_path_offset(blob
, "/soc8641");
139 addrcells
= (u32
*)fdt_getprop(blob
, 0, "#address-cells", NULL
);
140 tmp
= (u64
*)fdt_getprop(blob
, off
, "reg", NULL
);
144 if (addrcells
&& (*addrcells
== 1))
149 if (addr
!= CONFIG_SYS_CCSRBAR_PHYS
)
150 printf("WARNING: The CCSRBAR address in your .dts "
151 "does not match the address of the CCSR "
152 "in u-boot. This means your .dts might "
161 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
165 get_board_sys_clk(ulong dummy
)
167 u8 i
, go_bit
, rd_clks
;
169 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
171 go_bit
= in_8(pixis_base
+ PIXIS_VCTL
);
174 rd_clks
= in_8(pixis_base
+ PIXIS_VCFGEN0
);
178 * Only if both go bit and the SCLK bit in VCFGEN0 are set
179 * should we be using the AUX register. Remember, we also set the
180 * GO bit to boot from the alternate bank on the on-board flash
185 i
= in_8(pixis_base
+ PIXIS_AUX
);
187 i
= in_8(pixis_base
+ PIXIS_SPD
);
189 i
= in_8(pixis_base
+ PIXIS_SPD
);
224 int board_eth_init(bd_t
*bis
)
226 /* Initialize TSECs */
228 return pci_eth_init(bis
);
231 void board_reset(void)
233 u8
*pixis_base
= (u8
*)PIXIS_BASE
;
235 out_8(pixis_base
+ PIXIS_RST
, 0);