board/freescale/mpc8641hpcn/mpc8641hpcn.c

   1 /*
   2  * Copyright 2006, 2007, 2010-2011 Freescale Semiconductor.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <pci.h>
  25 #include <asm/processor.h>
  26 #include <asm/immap_86xx.h>
  27 #include <asm/fsl_pci.h>
  28 #include <asm/fsl_ddr_sdram.h>
  29 #include <asm/fsl_serdes.h>
  30 #include <asm/io.h>
  31 #include <libfdt.h>
  32 #include <fdt_support.h>
  33 #include <netdev.h>
  34
  35 phys_size_t fixed_sdram(void);
  36
  37 int checkboard(void)
  38 {
  39         u8 vboot;
  40         u8 *pixis_base = (u8 *)PIXIS_BASE;
  41
  42         printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, "
  43                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  44                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
  45                 in_8(pixis_base + PIXIS_PVER));
  46
  47         vboot = in_8(pixis_base + PIXIS_VBOOT);
  48         if (vboot & PIXIS_VBOOT_FMAP)
  49                 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
  50         else
  51                 puts ("Promjet\n");
  52
  53 #ifdef CONFIG_PHYS_64BIT
  54         printf ("       36-bit physical address map\n");
  55 #endif
  56         return 0;
  57 }
  58
  59 phys_size_t
  60 initdram(int board_type)
  61 {
  62         phys_size_t dram_size = 0;
  63
  64 #if defined(CONFIG_SPD_EEPROM)
  65         dram_size = fsl_ddr_sdram();
  66 #else
  67         dram_size = fixed_sdram();
  68 #endif
  69
  70         setup_ddr_bat(dram_size);
  71
  72         puts("    DDR: ");
  73         return dram_size;
  74 }
  75
  76
  77 #if !defined(CONFIG_SPD_EEPROM)
  78 /*
  79  * Fixed sdram init -- doesn't use serial presence detect.
  80  */
  81 phys_size_t
  82 fixed_sdram(void)
  83 {
  84 #if !defined(CONFIG_SYS_RAMBOOT)
  85         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  86         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
  87
  88         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  89         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  90         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  91         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  92         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  93         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  94         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  95         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  96         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  97         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  98         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  99         ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
 100         ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
 101
 102 #if defined (CONFIG_DDR_ECC)
 103         ddr->err_disable = 0x0000008D;
 104         ddr->err_sbe = 0x00ff0000;
 105 #endif
 106         asm("sync;isync");
 107
 108         udelay(500);
 109
 110 #if defined (CONFIG_DDR_ECC)
 111         /* Enable ECC checking */
 112         ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 113 #else
 114         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 115         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 116 #endif
 117         asm("sync; isync");
 118
 119         udelay(500);
 120 #endif
 121         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 122 }
 123 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 124
 125 void pci_init_board(void)
 126 {
 127         fsl_pcie_init_board(0);
 128
 129 #ifdef CONFIG_PCIE1
 130                 /*
 131                  * Activate ULI1575 legacy chip by performing a fake
 132                  * memory access.  Needed to make ULI RTC work.
 133                  */
 134                 in_be32((unsigned *) ((char *)(CONFIG_SYS_PCIE1_MEM_VIRT
 135                                        + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
 136 #endif /* CONFIG_PCIE1 */
 137 }
 138
 139
 140 #if defined(CONFIG_OF_BOARD_SETUP)
 141 void
 142 ft_board_setup(void *blob, bd_t *bd)
 143 {
 144         int off;
 145         u64 *tmp;
 146         u32 *addrcells;
 147
 148         ft_cpu_setup(blob, bd);
 149
 150         FT_FSL_PCI_SETUP;
 151
 152         /*
 153          * Warn if it looks like the device tree doesn't match u-boot.
 154          * This is just an estimation, based on the location of CCSR,
 155          * which is defined by the "reg" property in the soc node.
 156          */
 157         off = fdt_path_offset(blob, "/soc8641");
 158         addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
 159         tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
 160
 161         if (tmp) {
 162                 u64 addr;
 163                 if (addrcells && (*addrcells == 1))
 164                         addr = *(u32 *)tmp;
 165                 else
 166                         addr = *tmp;
 167
 168                 if (addr != CONFIG_SYS_CCSRBAR_PHYS)
 169                         printf("WARNING: The CCSRBAR address in your .dts "
 170                                "does not match the address of the CCSR "
 171                                "in u-boot.  This means your .dts might "
 172                                "be old.\n");
 173         }
 174 }
 175 #endif
 176
 177
 178 /*
 179  * get_board_sys_clk
 180  *      Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 181  */
 182
 183 unsigned long
 184 get_board_sys_clk(ulong dummy)
 185 {
 186         u8 i, go_bit, rd_clks;
 187         ulong val = 0;
 188         u8 *pixis_base = (u8 *)PIXIS_BASE;
 189
 190         go_bit = in_8(pixis_base + PIXIS_VCTL);
 191         go_bit &= 0x01;
 192
 193         rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
 194         rd_clks &= 0x1C;
 195
 196         /*
 197          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 198          * should we be using the AUX register. Remember, we also set the
 199          * GO bit to boot from the alternate bank on the on-board flash
 200          */
 201
 202         if (go_bit) {
 203                 if (rd_clks == 0x1c)
 204                         i = in_8(pixis_base + PIXIS_AUX);
 205                 else
 206                         i = in_8(pixis_base + PIXIS_SPD);
 207         } else {
 208                 i = in_8(pixis_base + PIXIS_SPD);
 209         }
 210
 211         i &= 0x07;
 212
 213         switch (i) {
 214         case 0:
 215                 val = 33000000;
 216                 break;
 217         case 1:
 218                 val = 40000000;
 219                 break;
 220         case 2:
 221                 val = 50000000;
 222                 break;
 223         case 3:
 224                 val = 66000000;
 225                 break;
 226         case 4:
 227                 val = 83000000;
 228                 break;
 229         case 5:
 230                 val = 100000000;
 231                 break;
 232         case 6:
 233                 val = 134000000;
 234                 break;
 235         case 7:
 236                 val = 166000000;
 237                 break;
 238         }
 239
 240         return val;
 241 }
 242
 243 int board_eth_init(bd_t *bis)
 244 {
 245         /* Initialize TSECs */
 246         cpu_eth_init(bis);
 247         return pci_eth_init(bis);
 248 }
 249
 250 void board_reset(void)
 251 {
 252         u8 *pixis_base = (u8 *)PIXIS_BASE;
 253
 254         out_8(pixis_base + PIXIS_RST, 0);
 255
 256         while (1)
 257                 ;
 258 }