2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/imx-regs.h>
29 DECLARE_GLOBAL_DATA_PTR
;
33 /* dram_init must store complete ramsize in gd->ram_size */
34 gd
->ram_size
= get_ram_size((volatile void *)PHYS_SDRAM_1
,
39 void dram_init_banksize(void)
41 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
42 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_1_SIZE
;
45 int board_early_init_f(void)
51 * CS0L and CS0A values are from the RedBoot sources by Freescale
52 * and are also equal to those used by Sascha Hauer for the Phytec
53 * i.MX31 board. CS0U is just a slightly optimized hardware default:
54 * the only non-zero field "Wait State Control" is set to half the
57 __REG(CSCR_U(0)) = 0x00000f00;
58 __REG(CSCR_L(0)) = 0x10000D03;
59 __REG(CSCR_A(0)) = 0x00720900;
61 /* setup pins for UART1 */
62 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX
);
63 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX
);
64 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B
);
65 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B
);
68 mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B
);
69 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK
);
70 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B
);
71 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI
);
72 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO
);
73 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B
);
74 mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B
);
76 /* start SPI2 clock */
77 __REG(CCM_CGR2
) = __REG(CCM_CGR2
) | (3 << 4);
80 /* Enable UART transceivers also reset the Ethernet/external UART */
83 writew(0x8023, CS4_BASE
+ 4);
85 /* RedBoot also has an empty loop with 100000 iterations here -
86 * clock doesn't run yet */
87 for (i
= 0; i
< 100000; i
++)
90 /* Clear the reset, toggle the LEDs */
91 writew(0xDF, CS4_BASE
+ 6);
93 /* clock still doesn't run */
94 for (i
= 0; i
< 100000; i
++)
97 /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
108 gd
->bd
->bi_arch_number
= MACH_TYPE_MX31ADS
; /* board id for linux */
109 gd
->bd
->bi_boot_params
= 0x80000100; /* adress of boot parameters */
114 int checkboard (void)
116 printf("Board: MX31ADS\n");
120 #ifdef CONFIG_CMD_NET
121 int board_eth_init(bd_t
*bis
)
125 rc
= cs8900_initialize(0, CONFIG_CS8900_BASE
);