board/freescale/mx31pdk/mx31pdk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *
   4  * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
   5  *
   6  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   7  */
   8
   9
  10 #include <common.h>
  11 #include <init.h>
  12 #include <net.h>
  13 #include <netdev.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <watchdog.h>
  18 #include <power/pmic.h>
  19 #include <fsl_pmic.h>
  20 #include <errno.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 #ifdef CONFIG_SPL_BUILD
  25 void board_init_f(ulong bootflag)
  26 {
  27         /*
  28          * copy ourselves from where we are running to where we were
  29          * linked at. Use ulong pointers as all addresses involved
  30          * are 4-byte-aligned.
  31          */
  32         ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
  33         asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
  34         asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
  35         asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
  36         asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
  37         for (dst = start_ptr; dst < end_ptr; dst++)
  38                 *dst = *(dst+(run_ptr-link_ptr));
  39         /*
  40          * branch to nand_boot's link-time address.
  41          */
  42         asm volatile("ldr pc, =nand_boot");
  43 }
  44 #endif
  45
  46 int dram_init(void)
  47 {
  48         /* dram_init must store complete ramsize in gd->ram_size */
  49         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  50                                 PHYS_SDRAM_1_SIZE);
  51         return 0;
  52 }
  53
  54 int board_early_init_f(void)
  55 {
  56         /* CS5: CPLD incl. network controller */
  57         static const struct mxc_weimcs cs5 = {
  58                 /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  59                 CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 24, 0,  4,  3),
  60                 /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  61                 CSCR_L(2,  2,   2,   5,  2,  0,  5,  2,  0,  0,   0,   1),
  62                 /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  63                 CSCR_A(2,   2,  2,  2,  0,  0,  2,  2,  0,  0,  0,  0,   0,  0)
  64         };
  65
  66         mxc_setup_weimcs(5, &cs5);
  67
  68         /* Setup UART1 and SPI2 pins */
  69         mx31_uart1_hw_init();
  70         mx31_spi2_hw_init();
  71
  72         return 0;
  73 }
  74
  75 int board_init(void)
  76 {
  77         /* adress of boot parameters */
  78         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  79
  80         return 0;
  81 }
  82
  83 int board_late_init(void)
  84 {
  85         u32 val;
  86         struct pmic *p;
  87         int ret;
  88
  89         ret = pmic_init(CONFIG_FSL_PMIC_BUS);
  90         if (ret)
  91                 return ret;
  92
  93         p = pmic_get("FSL_PMIC");
  94         if (!p)
  95                 return -ENODEV;
  96         /* Enable RTC battery */
  97         pmic_reg_read(p, REG_POWER_CTL0, &val);
  98         pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
  99         pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
 100 #ifdef CONFIG_HW_WATCHDOG
 101         hw_watchdog_init();
 102 #endif
 103         return 0;
 104 }
 105
 106 int checkboard(void)
 107 {
 108         printf("Board: MX31PDK\n");
 109         return 0;
 110 }
 111
 112 int board_eth_init(bd_t *bis)
 113 {
 114         int rc = 0;
 115 #ifdef CONFIG_SMC911X
 116         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 117 #endif
 118         return rc;
 119 }