board/freescale/mx35pdk/mx35pdk.c

   1 /*
   2  * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
   3  *
   4  * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/errno.h>
  28 #include <asm/arch/imx-regs.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <asm/arch/clock.h>
  31 #include <asm/arch/mx35_pins.h>
  32 #include <asm/arch/iomux.h>
  33 #include <i2c.h>
  34 #include <power/pmic.h>
  35 #include <fsl_pmic.h>
  36 #include <mmc.h>
  37 #include <fsl_esdhc.h>
  38 #include <mc9sdz60.h>
  39 #include <mc13892.h>
  40 #include <linux/types.h>
  41 #include <asm/gpio.h>
  42 #include <asm/arch/sys_proto.h>
  43 #include <netdev.h>
  44
  45 #ifndef CONFIG_BOARD_LATE_INIT
  46 #error "CONFIG_BOARD_LATE_INIT must be set for this board"
  47 #endif
  48
  49 #ifndef CONFIG_BOARD_EARLY_INIT_F
  50 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
  51 #endif
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 int dram_init(void)
  56 {
  57         u32 size1, size2;
  58
  59         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  60         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  61
  62         gd->ram_size = size1 + size2;
  63
  64         return 0;
  65 }
  66
  67 void dram_init_banksize(void)
  68 {
  69         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  70         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  71
  72         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  73         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  74 }
  75
  76 static void setup_iomux_i2c(void)
  77 {
  78         int pad;
  79
  80         /* setup pins for I2C1 */
  81         mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
  82         mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
  83
  84         pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
  85                         | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
  86
  87         mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
  88         mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
  89 }
  90
  91
  92 static void setup_iomux_spi(void)
  93 {
  94         mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
  95         mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
  96         mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
  97         mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
  98         mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
  99 }
 100
 101 static void setup_iomux_usbotg(void)
 102 {
 103         int in_pad, out_pad;
 104
 105         /* Set up pins for USBOTG. */
 106         mxc_request_iomux(MX35_PIN_USBOTG_PWR,
 107                           MUX_CONFIG_SION | MUX_CONFIG_FUNC);
 108         mxc_request_iomux(MX35_PIN_USBOTG_OC,
 109                           MUX_CONFIG_SION | MUX_CONFIG_FUNC);
 110
 111         in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
 112                 PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
 113                 PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
 114         out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
 115                 PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
 116
 117         mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
 118         mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
 119 }
 120
 121 static void setup_iomux_fec(void)
 122 {
 123         int pad;
 124
 125         /* setup pins for FEC */
 126         mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
 127         mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
 128         mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
 129         mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
 130         mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
 131         mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
 132         mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
 133         mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
 134         mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
 135         mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
 136         mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
 137         mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
 138         mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
 139         mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
 140         mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
 141         mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
 142         mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
 143         mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
 144
 145         pad = (PAD_CTL_DRV_3_3V | PAD_CTL_PUE_PUD | PAD_CTL_ODE_CMOS | \
 146                         PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW);
 147
 148         mxc_iomux_set_pad(MX35_PIN_FEC_TX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
 149                         PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 150         mxc_iomux_set_pad(MX35_PIN_FEC_RX_CLK, pad | PAD_CTL_HYS_SCHMITZ | \
 151                         PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 152         mxc_iomux_set_pad(MX35_PIN_FEC_RX_DV, pad | PAD_CTL_HYS_SCHMITZ | \
 153                          PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 154         mxc_iomux_set_pad(MX35_PIN_FEC_COL, pad | PAD_CTL_HYS_SCHMITZ | \
 155                           PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 156         mxc_iomux_set_pad(MX35_PIN_FEC_RDATA0, pad | PAD_CTL_HYS_SCHMITZ | \
 157                           PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 158         mxc_iomux_set_pad(MX35_PIN_FEC_TDATA0, pad | PAD_CTL_HYS_CMOS | \
 159                           PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
 160         mxc_iomux_set_pad(MX35_PIN_FEC_TX_EN, pad | PAD_CTL_HYS_CMOS | \
 161                           PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
 162         mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad | PAD_CTL_HYS_CMOS | \
 163                           PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
 164         mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad | PAD_CTL_HYS_SCHMITZ | \
 165                           PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU);
 166         mxc_iomux_set_pad(MX35_PIN_FEC_TX_ERR, pad | PAD_CTL_HYS_CMOS | \
 167                           PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
 168         mxc_iomux_set_pad(MX35_PIN_FEC_RX_ERR, pad | PAD_CTL_HYS_SCHMITZ | \
 169                           PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 170         mxc_iomux_set_pad(MX35_PIN_FEC_CRS, pad | PAD_CTL_HYS_SCHMITZ | \
 171                           PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 172         mxc_iomux_set_pad(MX35_PIN_FEC_RDATA1, pad | PAD_CTL_HYS_SCHMITZ | \
 173                           PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 174         mxc_iomux_set_pad(MX35_PIN_FEC_TDATA1, pad | PAD_CTL_HYS_CMOS | \
 175                           PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
 176         mxc_iomux_set_pad(MX35_PIN_FEC_RDATA2, pad | PAD_CTL_HYS_SCHMITZ | \
 177                           PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 178         mxc_iomux_set_pad(MX35_PIN_FEC_TDATA2, pad | PAD_CTL_HYS_CMOS | \
 179                           PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
 180         mxc_iomux_set_pad(MX35_PIN_FEC_RDATA3, pad | PAD_CTL_HYS_SCHMITZ | \
 181                           PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PD);
 182         mxc_iomux_set_pad(MX35_PIN_FEC_TDATA3, pad | PAD_CTL_HYS_CMOS | \
 183                           PAD_CTL_PKE_NONE | PAD_CTL_100K_PD);
 184 }
 185
 186 int board_early_init_f(void)
 187 {
 188         struct ccm_regs *ccm =
 189                 (struct ccm_regs *)IMX_CCM_BASE;
 190
 191         /* enable clocks */
 192         writel(readl(&ccm->cgr0) |
 193                 MXC_CCM_CGR0_EMI_MASK |
 194                 MXC_CCM_CGR0_EDIO_MASK |
 195                 MXC_CCM_CGR0_EPIT1_MASK,
 196                 &ccm->cgr0);
 197
 198         writel(readl(&ccm->cgr1) |
 199                 MXC_CCM_CGR1_FEC_MASK |
 200                 MXC_CCM_CGR1_GPIO1_MASK |
 201                 MXC_CCM_CGR1_GPIO2_MASK |
 202                 MXC_CCM_CGR1_GPIO3_MASK |
 203                 MXC_CCM_CGR1_I2C1_MASK |
 204                 MXC_CCM_CGR1_I2C2_MASK |
 205                 MXC_CCM_CGR1_IPU_MASK,
 206                 &ccm->cgr1);
 207
 208         /* Setup NAND */
 209         __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 210
 211         setup_iomux_i2c();
 212         setup_iomux_usbotg();
 213         setup_iomux_fec();
 214         setup_iomux_spi();
 215
 216         return 0;
 217 }
 218
 219 int board_init(void)
 220 {
 221         gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS;    /* board id for linux */
 222         /* address of boot parameters */
 223         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 224
 225         return 0;
 226 }
 227
 228 static inline int pmic_detect(void)
 229 {
 230         unsigned int id;
 231         struct pmic *p = pmic_get("FSL_PMIC");
 232         if (!p)
 233                 return -ENODEV;
 234
 235         pmic_reg_read(p, REG_IDENTIFICATION, &id);
 236
 237         id = (id >> 6) & 0x7;
 238         if (id == 0x7)
 239                 return 1;
 240         return 0;
 241 }
 242
 243 u32 get_board_rev(void)
 244 {
 245         int rev;
 246
 247         rev = pmic_detect();
 248
 249         return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 250 }
 251
 252 int board_late_init(void)
 253 {
 254         u8 val;
 255         u32 pmic_val;
 256         struct pmic *p;
 257         int ret;
 258
 259         ret = pmic_init(I2C_PMIC);
 260         if (ret)
 261                 return ret;
 262
 263         if (pmic_detect()) {
 264                 p = pmic_get("FSL_PMIC");
 265                 mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION |
 266                                         MUX_CONFIG_ALT1);
 267
 268                 pmic_reg_read(p, REG_SETTING_0, &pmic_val);
 269                 pmic_reg_write(p, REG_SETTING_0,
 270                         pmic_val | VO_1_30V | VO_1_50V);
 271                 pmic_reg_read(p, REG_MODE_0, &pmic_val);
 272                 pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
 273
 274                 mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
 275                 mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
 276
 277                 gpio_direction_output(37, 1);
 278         }
 279
 280         val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
 281         mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
 282         mdelay(200);
 283
 284         val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
 285         mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
 286         mdelay(200);
 287
 288         val |= 0x80;
 289         mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
 290
 291         /* Print board revision */
 292         printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
 293
 294         return 0;
 295 }
 296
 297 int board_eth_init(bd_t *bis)
 298 {
 299         int rc = -ENODEV;
 300 #if defined(CONFIG_SMC911X)
 301         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 302 #endif
 303
 304         cpu_eth_init(bis);
 305
 306         return rc;
 307 }
 308
 309 #if defined(CONFIG_FSL_ESDHC)
 310
 311 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
 312
 313 int board_mmc_init(bd_t *bis)
 314 {
 315         /* configure pins for SDHC1 only */
 316         mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
 317         mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
 318         mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
 319         mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
 320         mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
 321         mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
 322
 323         esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 324         return fsl_esdhc_initialize(bis, &esdhc_cfg);
 325 }
 326
 327 int board_mmc_getcd(struct mmc *mmc)
 328 {
 329         return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
 330 }
 331 #endif