board/freescale/mx53evk/mx53evk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2010 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/sys_proto.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/iomux-mx53.h>
  13 #include <linux/errno.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15 #include <netdev.h>
  16 #include <i2c.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc.h>
  19 #include <power/pmic.h>
  20 #include <fsl_pmic.h>
  21 #include <asm/gpio.h>
  22 #include <mc13892.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 int dram_init(void)
  27 {
  28         /* dram_init must store complete ramsize in gd->ram_size */
  29         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  30                                 PHYS_SDRAM_1_SIZE);
  31         return 0;
  32 }
  33
  34 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  35                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  36
  37 static void setup_iomux_uart(void)
  38 {
  39         static const iomux_v3_cfg_t uart_pads[] = {
  40                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
  41                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
  42         };
  43
  44         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  45 }
  46
  47 #define I2C_PAD_CTRL    (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  48                          PAD_CTL_HYS | PAD_CTL_ODE)
  49
  50 static void setup_i2c(unsigned int port_number)
  51 {
  52         static const iomux_v3_cfg_t i2c1_pads[] = {
  53                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
  54                 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
  55         };
  56
  57         static const iomux_v3_cfg_t i2c2_pads[] = {
  58                 NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
  59                 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
  60         };
  61
  62         switch (port_number) {
  63         case 0:
  64                 imx_iomux_v3_setup_multiple_pads(i2c1_pads,
  65                                                         ARRAY_SIZE(i2c1_pads));
  66                 break;
  67         case 1:
  68                 imx_iomux_v3_setup_multiple_pads(i2c2_pads,
  69                                                         ARRAY_SIZE(i2c2_pads));
  70                 break;
  71         default:
  72                 printf("Warning: Wrong I2C port number\n");
  73                 break;
  74         }
  75 }
  76
  77 void power_init(void)
  78 {
  79         unsigned int val;
  80         struct pmic *p;
  81         int ret;
  82
  83         ret = pmic_init(I2C_0);
  84         if (ret)
  85                 return;
  86
  87         p = pmic_get("FSL_PMIC");
  88         if (!p)
  89                 return;
  90
  91         /* Set VDDA to 1.25V */
  92         pmic_reg_read(p, REG_SW_2, &val);
  93         val &= ~SWX_OUT_MASK;
  94         val |= SWX_OUT_1_25;
  95         pmic_reg_write(p, REG_SW_2, val);
  96
  97         /*
  98          * Need increase VCC and VDDA to 1.3V
  99          * according to MX53 IC TO2 datasheet.
 100          */
 101         if (is_soc_rev(CHIP_REV_2_0) == 0) {
 102                 /* Set VCC to 1.3V for TO2 */
 103                 pmic_reg_read(p, REG_SW_1, &val);
 104                 val &= ~SWX_OUT_MASK;
 105                 val |= SWX_OUT_1_30;
 106                 pmic_reg_write(p, REG_SW_1, val);
 107
 108                 /* Set VDDA to 1.3V for TO2 */
 109                 pmic_reg_read(p, REG_SW_2, &val);
 110                 val &= ~SWX_OUT_MASK;
 111                 val |= SWX_OUT_1_30;
 112                 pmic_reg_write(p, REG_SW_2, val);
 113         }
 114 }
 115
 116 static void setup_iomux_fec(void)
 117 {
 118         static const iomux_v3_cfg_t fec_pads[] = {
 119                 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
 120                         PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
 121                 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
 122                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
 123                                 PAD_CTL_HYS | PAD_CTL_PKE),
 124                 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
 125                                 PAD_CTL_HYS | PAD_CTL_PKE),
 126                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
 127                 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
 128                 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
 129                 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
 130                                 PAD_CTL_HYS | PAD_CTL_PKE),
 131                 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
 132                                 PAD_CTL_HYS | PAD_CTL_PKE),
 133                 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
 134                                 PAD_CTL_HYS | PAD_CTL_PKE),
 135         };
 136
 137         imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 138 }
 139
 140 #ifdef CONFIG_FSL_ESDHC
 141 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 142         {MMC_SDHC1_BASE_ADDR},
 143         {MMC_SDHC3_BASE_ADDR},
 144 };
 145
 146 int board_mmc_getcd(struct mmc *mmc)
 147 {
 148         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 149         int ret;
 150
 151         imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
 152         gpio_direction_input(IMX_GPIO_NR(3, 11));
 153         imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
 154         gpio_direction_input(IMX_GPIO_NR(3, 13));
 155
 156         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 157                 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
 158         else
 159                 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
 160
 161         return ret;
 162 }
 163
 164 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 165                                  PAD_CTL_PUS_100K_UP)
 166 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 167                                  PAD_CTL_DSE_HIGH)
 168
 169 int board_mmc_init(bd_t *bis)
 170 {
 171         static const iomux_v3_cfg_t sd1_pads[] = {
 172                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 173                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
 174                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 175                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 176                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 177                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 178                 MX53_PAD_EIM_DA13__GPIO3_13,
 179         };
 180
 181         static const iomux_v3_cfg_t sd2_pads[] = {
 182                 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
 183                                 SD_CMD_PAD_CTRL),
 184                 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
 185                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
 186                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
 187                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
 188                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
 189                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
 190                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
 191                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
 192                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
 193                 MX53_PAD_EIM_DA11__GPIO3_11,
 194         };
 195
 196         u32 index;
 197         int ret;
 198
 199         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 200         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 201
 202         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 203                 switch (index) {
 204                 case 0:
 205                         imx_iomux_v3_setup_multiple_pads(sd1_pads,
 206                                                          ARRAY_SIZE(sd1_pads));
 207                         break;
 208                 case 1:
 209                         imx_iomux_v3_setup_multiple_pads(sd2_pads,
 210                                                          ARRAY_SIZE(sd2_pads));
 211                         break;
 212                 default:
 213                         printf("Warning: you configured more ESDHC controller"
 214                                 "(%d) as supported by the board(2)\n",
 215                                 CONFIG_SYS_FSL_ESDHC_NUM);
 216                         return -EINVAL;
 217                 }
 218                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 219                 if (ret)
 220                         return ret;
 221         }
 222
 223         return 0;
 224 }
 225 #endif
 226
 227 int board_early_init_f(void)
 228 {
 229         setup_iomux_uart();
 230         setup_iomux_fec();
 231
 232         return 0;
 233 }
 234
 235 int board_init(void)
 236 {
 237         /* address of boot parameters */
 238         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 239
 240         return 0;
 241 }
 242
 243 #ifdef CONFIG_CMD_BMODE
 244 static const struct boot_mode board_boot_modes[] = {
 245         /* 4 bit bus width */
 246         {"mmc0",        MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
 247         {"mmc1",        MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
 248         {NULL,          0},
 249 };
 250 #endif
 251
 252 int board_late_init(void)
 253 {
 254         setup_i2c(1);
 255         power_init();
 256
 257 #ifdef CONFIG_CMD_BMODE
 258         add_board_boot_modes(board_boot_modes);
 259 #endif
 260         return 0;
 261 }
 262
 263 int checkboard(void)
 264 {
 265         puts("Board: MX53EVK\n");
 266
 267         return 0;
 268 }