2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/mx5x_pins.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/arch/clock.h>
31 #include <asm/arch/iomux.h>
32 #include <asm/arch/clock.h>
33 #include <asm/errno.h>
37 #include <fsl_esdhc.h>
40 #include <dialog_pmic.h>
42 DECLARE_GLOBAL_DATA_PTR
;
48 size1
= get_ram_size((void *)PHYS_SDRAM_1
, PHYS_SDRAM_1_SIZE
);
49 size2
= get_ram_size((void *)PHYS_SDRAM_2
, PHYS_SDRAM_2_SIZE
);
51 gd
->ram_size
= size1
+ size2
;
55 void dram_init_banksize(void)
57 gd
->bd
->bi_dram
[0].start
= PHYS_SDRAM_1
;
58 gd
->bd
->bi_dram
[0].size
= PHYS_SDRAM_1_SIZE
;
60 gd
->bd
->bi_dram
[1].start
= PHYS_SDRAM_2
;
61 gd
->bd
->bi_dram
[1].size
= PHYS_SDRAM_2_SIZE
;
64 static void setup_iomux_uart(void)
67 mxc_request_iomux(MX53_PIN_CSI0_D11
, IOMUX_CONFIG_ALT2
);
68 mxc_iomux_set_pad(MX53_PIN_CSI0_D11
,
69 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
70 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
71 PAD_CTL_HYS_ENABLE
| PAD_CTL_100K_PU
|
72 PAD_CTL_ODE_OPENDRAIN_ENABLE
);
73 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT
, 0x1);
76 mxc_request_iomux(MX53_PIN_CSI0_D10
, IOMUX_CONFIG_ALT2
);
77 mxc_iomux_set_pad(MX53_PIN_CSI0_D10
,
78 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
79 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
80 PAD_CTL_HYS_ENABLE
| PAD_CTL_100K_PU
|
81 PAD_CTL_ODE_OPENDRAIN_ENABLE
);
84 #ifdef CONFIG_USB_EHCI_MX5
85 int board_ehci_hcd_init(int port
)
87 /* request VBUS power enable pin, GPIO[8}, gpio7 */
88 mxc_request_iomux(MX53_PIN_ATA_DA_2
, IOMUX_CONFIG_ALT1
);
89 gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2
), 0);
90 gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2
), 1);
95 static void setup_iomux_fec(void)
98 mxc_request_iomux(MX53_PIN_FEC_MDIO
, IOMUX_CONFIG_ALT0
);
99 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO
,
100 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
101 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
102 PAD_CTL_22K_PU
| PAD_CTL_ODE_OPENDRAIN_ENABLE
);
103 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT
, 0x1);
106 mxc_request_iomux(MX53_PIN_FEC_MDC
, IOMUX_CONFIG_ALT0
);
107 mxc_iomux_set_pad(MX53_PIN_FEC_MDC
, PAD_CTL_DRV_HIGH
);
110 mxc_request_iomux(MX53_PIN_FEC_RXD1
, IOMUX_CONFIG_ALT0
);
111 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1
,
112 PAD_CTL_HYS_ENABLE
| PAD_CTL_PKE_ENABLE
);
115 mxc_request_iomux(MX53_PIN_FEC_RXD0
, IOMUX_CONFIG_ALT0
);
116 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0
,
117 PAD_CTL_HYS_ENABLE
| PAD_CTL_PKE_ENABLE
);
120 mxc_request_iomux(MX53_PIN_FEC_TXD1
, IOMUX_CONFIG_ALT0
);
121 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1
, PAD_CTL_DRV_HIGH
);
124 mxc_request_iomux(MX53_PIN_FEC_TXD0
, IOMUX_CONFIG_ALT0
);
125 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0
, PAD_CTL_DRV_HIGH
);
128 mxc_request_iomux(MX53_PIN_FEC_TX_EN
, IOMUX_CONFIG_ALT0
);
129 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN
, PAD_CTL_DRV_HIGH
);
132 mxc_request_iomux(MX53_PIN_FEC_REF_CLK
, IOMUX_CONFIG_ALT0
);
133 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK
,
134 PAD_CTL_HYS_ENABLE
| PAD_CTL_PKE_ENABLE
);
137 mxc_request_iomux(MX53_PIN_FEC_RX_ER
, IOMUX_CONFIG_ALT0
);
138 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER
,
139 PAD_CTL_HYS_ENABLE
| PAD_CTL_PKE_ENABLE
);
142 mxc_request_iomux(MX53_PIN_FEC_CRS_DV
, IOMUX_CONFIG_ALT0
);
143 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV
,
144 PAD_CTL_HYS_ENABLE
| PAD_CTL_PKE_ENABLE
);
147 #ifdef CONFIG_FSL_ESDHC
148 struct fsl_esdhc_cfg esdhc_cfg
[2] = {
149 {MMC_SDHC1_BASE_ADDR
, 1},
150 {MMC_SDHC3_BASE_ADDR
, 1},
153 int board_mmc_getcd(struct mmc
*mmc
)
155 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
158 mxc_request_iomux(MX53_PIN_EIM_DA11
, IOMUX_CONFIG_ALT1
);
159 gpio_direction_input(75);
160 mxc_request_iomux(MX53_PIN_EIM_DA13
, IOMUX_CONFIG_ALT1
);
161 gpio_direction_input(77);
163 if (cfg
->esdhc_base
== MMC_SDHC1_BASE_ADDR
)
164 ret
= !gpio_get_value(77); /* GPIO3_13 */
166 ret
= !gpio_get_value(75); /* GPIO3_11 */
171 int board_mmc_init(bd_t
*bis
)
176 for (index
= 0; index
< CONFIG_SYS_FSL_ESDHC_NUM
; index
++) {
179 mxc_request_iomux(MX53_PIN_SD1_CMD
, IOMUX_CONFIG_ALT0
);
180 mxc_request_iomux(MX53_PIN_SD1_CLK
, IOMUX_CONFIG_ALT0
);
181 mxc_request_iomux(MX53_PIN_SD1_DATA0
,
183 mxc_request_iomux(MX53_PIN_SD1_DATA1
,
185 mxc_request_iomux(MX53_PIN_SD1_DATA2
,
187 mxc_request_iomux(MX53_PIN_SD1_DATA3
,
189 mxc_request_iomux(MX53_PIN_EIM_DA13
,
192 mxc_iomux_set_pad(MX53_PIN_SD1_CMD
,
193 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
194 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
195 PAD_CTL_HYS_ENABLE
| PAD_CTL_100K_PU
);
196 mxc_iomux_set_pad(MX53_PIN_SD1_CLK
,
197 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
198 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
|
200 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0
,
201 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
202 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
203 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
204 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1
,
205 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
206 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
207 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
208 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2
,
209 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
210 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
211 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
212 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3
,
213 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
214 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
215 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
218 mxc_request_iomux(MX53_PIN_ATA_RESET_B
,
220 mxc_request_iomux(MX53_PIN_ATA_IORDY
,
222 mxc_request_iomux(MX53_PIN_ATA_DATA8
,
224 mxc_request_iomux(MX53_PIN_ATA_DATA9
,
226 mxc_request_iomux(MX53_PIN_ATA_DATA10
,
228 mxc_request_iomux(MX53_PIN_ATA_DATA11
,
230 mxc_request_iomux(MX53_PIN_ATA_DATA0
,
232 mxc_request_iomux(MX53_PIN_ATA_DATA1
,
234 mxc_request_iomux(MX53_PIN_ATA_DATA2
,
236 mxc_request_iomux(MX53_PIN_ATA_DATA3
,
238 mxc_request_iomux(MX53_PIN_EIM_DA11
,
241 mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B
,
242 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
243 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
244 PAD_CTL_HYS_ENABLE
| PAD_CTL_100K_PU
);
245 mxc_iomux_set_pad(MX53_PIN_ATA_IORDY
,
246 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
247 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
|
249 mxc_iomux_set_pad(MX53_PIN_ATA_DATA8
,
250 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
251 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
252 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
253 mxc_iomux_set_pad(MX53_PIN_ATA_DATA9
,
254 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
255 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
256 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
257 mxc_iomux_set_pad(MX53_PIN_ATA_DATA10
,
258 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
259 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
260 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
261 mxc_iomux_set_pad(MX53_PIN_ATA_DATA11
,
262 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
263 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
264 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
265 mxc_iomux_set_pad(MX53_PIN_ATA_DATA0
,
266 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
267 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
268 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
269 mxc_iomux_set_pad(MX53_PIN_ATA_DATA1
,
270 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
271 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
272 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
273 mxc_iomux_set_pad(MX53_PIN_ATA_DATA2
,
274 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
275 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
276 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
277 mxc_iomux_set_pad(MX53_PIN_ATA_DATA3
,
278 PAD_CTL_HYS_ENABLE
| PAD_CTL_DRV_HIGH
|
279 PAD_CTL_PUE_PULL
| PAD_CTL_PKE_ENABLE
|
280 PAD_CTL_HYS_ENABLE
| PAD_CTL_47K_PU
);
284 printf("Warning: you configured more ESDHC controller"
285 "(%d) as supported by the board(2)\n",
286 CONFIG_SYS_FSL_ESDHC_NUM
);
289 status
|= fsl_esdhc_initialize(bis
, &esdhc_cfg
[index
]);
296 static void setup_iomux_i2c(void)
299 mxc_request_iomux(MX53_PIN_CSI0_D8
,
300 IOMUX_CONFIG_ALT5
| IOMUX_CONFIG_SION
);
301 mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT
,
303 mxc_iomux_set_pad(MX53_PIN_CSI0_D8
,
304 PAD_CTL_SRE_FAST
| PAD_CTL_DRV_HIGH
|
305 PAD_CTL_100K_PU
| PAD_CTL_PKE_ENABLE
|
307 PAD_CTL_ODE_OPENDRAIN_ENABLE
);
309 mxc_request_iomux(MX53_PIN_CSI0_D9
,
310 IOMUX_CONFIG_ALT5
| IOMUX_CONFIG_SION
);
311 mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT
,
313 mxc_iomux_set_pad(MX53_PIN_CSI0_D9
,
314 PAD_CTL_SRE_FAST
| PAD_CTL_DRV_HIGH
|
315 PAD_CTL_100K_PU
| PAD_CTL_PKE_ENABLE
|
317 PAD_CTL_ODE_OPENDRAIN_ENABLE
);
320 static int power_init(void)
322 unsigned int val
, ret
;
328 /* Set VDDA to 1.25V */
329 val
= DA9052_BUCKCORE_BCOREEN
| DA_BUCKCORE_VBCORE_1_250V
;
330 ret
= pmic_reg_write(p
, DA9053_BUCKCORE_REG
, val
);
332 ret
|= pmic_reg_read(p
, DA9053_SUPPLY_REG
, &val
);
333 val
|= DA9052_SUPPLY_VBCOREGO
;
334 ret
|= pmic_reg_write(p
, DA9053_SUPPLY_REG
, val
);
336 /* Set Vcc peripheral to 1.35V */
337 ret
|= pmic_reg_write(p
, DA9053_BUCKPRO_REG
, 0x62);
338 ret
|= pmic_reg_write(p
, DA9053_SUPPLY_REG
, 0x62);
343 static void clock_1GHz(void)
346 u32 ref_clk
= CONFIG_SYS_MX5_HCLK
;
348 * After increasing voltage to 1.25V, we can switch
349 * CPU clock to 1GHz and DDR to 400MHz safely
351 ret
= mxc_set_clock(ref_clk
, 1000, MXC_ARM_CLK
);
353 printf("CPU: Switch CPU clock to 1GHZ failed\n");
355 ret
= mxc_set_clock(ref_clk
, 400, MXC_PERIPH_CLK
);
356 ret
|= mxc_set_clock(ref_clk
, 400, MXC_DDR_CLK
);
358 printf("CPU: Switch DDR clock to 400MHz failed\n");
361 int board_early_init_f(void)
369 int print_cpuinfo(void)
373 cpurev
= get_cpu_rev();
374 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
375 (cpurev
& 0xFF000) >> 12,
376 (cpurev
& 0x000F0) >> 4,
377 (cpurev
& 0x0000F) >> 0,
378 mxc_get_clock(MXC_ARM_CLK
) / 1000000);
379 printf("Reset cause: %s\n", get_reset_cause());
383 #ifdef CONFIG_BOARD_LATE_INIT
384 int board_late_init(void)
397 gd
->bd
->bi_boot_params
= PHYS_SDRAM_1
+ 0x100;
399 mxc_set_sata_internal_clock();
406 puts("Board: MX53 LOCO\n");