board/freescale/mx6qsabrelite/mx6qsabrelite.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/iomux.h>
  28 #include <asm/arch/mx6x_pins.h>
  29 #include <asm/errno.h>
  30 #include <asm/gpio.h>
  31 #include <asm/imx-common/iomux-v3.h>
  32 #include <asm/imx-common/mxc_i2c.h>
  33 #include <asm/imx-common/boot_mode.h>
  34 #include <mmc.h>
  35 #include <fsl_esdhc.h>
  36 #include <micrel.h>
  37 #include <miiphy.h>
  38 #include <netdev.h>
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
  42        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  43        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  46        PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  47        PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  50         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  51         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  52
  53 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  54         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  55         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  56
  57 #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  58         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  59         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  60
  61 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  62         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  63         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  64         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  65
  66 int dram_init(void)
  67 {
  68        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  69
  70        return 0;
  71 }
  72
  73 iomux_v3_cfg_t const uart1_pads[] = {
  74         MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  75         MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  76 };
  77
  78 iomux_v3_cfg_t const uart2_pads[] = {
  79        MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  80        MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  81 };
  82
  83 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  84
  85 /* I2C1, SGTL5000 */
  86 struct i2c_pads_info i2c_pad_info0 = {
  87         .scl = {
  88                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
  89                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
  90                 .gp = IMX_GPIO_NR(3, 21)
  91         },
  92         .sda = {
  93                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
  94                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
  95                 .gp = IMX_GPIO_NR(3, 28)
  96         }
  97 };
  98
  99 /* I2C2 Camera, MIPI */
 100 struct i2c_pads_info i2c_pad_info1 = {
 101         .scl = {
 102                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 103                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
 104                 .gp = IMX_GPIO_NR(4, 12)
 105         },
 106         .sda = {
 107                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 108                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
 109                 .gp = IMX_GPIO_NR(4, 13)
 110         }
 111 };
 112
 113 /* I2C3, J15 - RGB connector */
 114 struct i2c_pads_info i2c_pad_info2 = {
 115         .scl = {
 116                 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
 117                 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
 118                 .gp = IMX_GPIO_NR(1, 5)
 119         },
 120         .sda = {
 121                 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
 122                 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
 123                 .gp = IMX_GPIO_NR(7, 11)
 124         }
 125 };
 126
 127 iomux_v3_cfg_t const usdhc3_pads[] = {
 128        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130        MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131        MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132        MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133        MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134        MX6Q_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 135 };
 136
 137 iomux_v3_cfg_t const usdhc4_pads[] = {
 138        MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139        MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140        MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141        MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142        MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143        MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144        MX6Q_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 145 };
 146
 147 iomux_v3_cfg_t const enet_pads1[] = {
 148         MX6Q_PAD_ENET_MDIO__ENET_MDIO           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 149         MX6Q_PAD_ENET_MDC__ENET_MDC             | MUX_PAD_CTRL(ENET_PAD_CTRL),
 150         MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 151         MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 152         MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 153         MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 154         MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 155         MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL     | MUX_PAD_CTRL(ENET_PAD_CTRL),
 156         MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 157         /* pin 35 - 1 (PHY_AD2) on reset */
 158         MX6Q_PAD_RGMII_RXC__GPIO_6_30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 159         /* pin 32 - 1 - (MODE0) all */
 160         MX6Q_PAD_RGMII_RD0__GPIO_6_25           | MUX_PAD_CTRL(NO_PAD_CTRL),
 161         /* pin 31 - 1 - (MODE1) all */
 162         MX6Q_PAD_RGMII_RD1__GPIO_6_27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 163         /* pin 28 - 1 - (MODE2) all */
 164         MX6Q_PAD_RGMII_RD2__GPIO_6_28           | MUX_PAD_CTRL(NO_PAD_CTRL),
 165         /* pin 27 - 1 - (MODE3) all */
 166         MX6Q_PAD_RGMII_RD3__GPIO_6_29           | MUX_PAD_CTRL(NO_PAD_CTRL),
 167         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 168         MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24        | MUX_PAD_CTRL(NO_PAD_CTRL),
 169         /* pin 42 PHY nRST */
 170         MX6Q_PAD_EIM_D23__GPIO_3_23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 171 };
 172
 173 iomux_v3_cfg_t const enet_pads2[] = {
 174         MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 175         MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 176         MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 177         MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 178         MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 179         MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL     | MUX_PAD_CTRL(ENET_PAD_CTRL),
 180 };
 181
 182 /* Button assignments for J14 */
 183 static iomux_v3_cfg_t const button_pads[] = {
 184         /* Menu */
 185         MX6Q_PAD_NANDF_D1__GPIO_2_1     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 186         /* Back */
 187         MX6Q_PAD_NANDF_D2__GPIO_2_2     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 188         /* Labelled Search (mapped to Power under Android) */
 189         MX6Q_PAD_NANDF_D3__GPIO_2_3     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 190         /* Home */
 191         MX6Q_PAD_NANDF_D4__GPIO_2_4     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 192         /* Volume Down */
 193         MX6Q_PAD_GPIO_19__GPIO_4_5      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 194         /* Volume Up */
 195         MX6Q_PAD_GPIO_18__GPIO_7_13     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 196 };
 197
 198 static void setup_iomux_enet(void)
 199 {
 200         gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
 201         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 202         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 203         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 204         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 205         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 206         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 207         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 208
 209         /* Need delay 10ms according to KSZ9021 spec */
 210         udelay(1000 * 10);
 211         gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 212
 213         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 214 }
 215
 216 iomux_v3_cfg_t const usb_pads[] = {
 217         MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 218 };
 219
 220 static void setup_iomux_uart(void)
 221 {
 222         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 223        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 224 }
 225
 226 #ifdef CONFIG_USB_EHCI_MX6
 227 int board_ehci_hcd_init(int port)
 228 {
 229         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 230
 231         /* Reset USB hub */
 232         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 233         mdelay(2);
 234         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 235
 236         return 0;
 237 }
 238 #endif
 239
 240 #ifdef CONFIG_FSL_ESDHC
 241 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 242        {USDHC3_BASE_ADDR},
 243        {USDHC4_BASE_ADDR},
 244 };
 245
 246 int board_mmc_getcd(struct mmc *mmc)
 247 {
 248        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 249        int ret;
 250
 251        if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 252                 gpio_direction_input(IMX_GPIO_NR(7, 0));
 253                 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
 254        } else {
 255                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 256                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 257        }
 258
 259        return ret;
 260 }
 261
 262 int board_mmc_init(bd_t *bis)
 263 {
 264        s32 status = 0;
 265        u32 index = 0;
 266
 267         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 268         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 269
 270        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 271                switch (index) {
 272                case 0:
 273                        imx_iomux_v3_setup_multiple_pads(
 274                                usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 275                        break;
 276                case 1:
 277                        imx_iomux_v3_setup_multiple_pads(
 278                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 279                        break;
 280                default:
 281                        printf("Warning: you configured more USDHC controllers"
 282                                "(%d) then supported by the board (%d)\n",
 283                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 284                        return status;
 285                }
 286
 287                status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 288        }
 289
 290        return status;
 291 }
 292 #endif
 293
 294 u32 get_board_rev(void)
 295 {
 296         return 0x63000 ;
 297 }
 298
 299 #ifdef CONFIG_MXC_SPI
 300 iomux_v3_cfg_t const ecspi1_pads[] = {
 301         /* SS1 */
 302         MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 303         MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 304         MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 305         MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 306 };
 307
 308 void setup_spi(void)
 309 {
 310         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 311         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 312                                          ARRAY_SIZE(ecspi1_pads));
 313 }
 314 #endif
 315
 316 int board_phy_config(struct phy_device *phydev)
 317 {
 318         /* min rx data delay */
 319         ksz9021_phy_extended_write(phydev,
 320                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 321         /* min tx data delay */
 322         ksz9021_phy_extended_write(phydev,
 323                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 324         /* max rx/tx clock delay, min rx/tx control */
 325         ksz9021_phy_extended_write(phydev,
 326                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 327         if (phydev->drv->config)
 328                 phydev->drv->config(phydev);
 329
 330         return 0;
 331 }
 332
 333 int board_eth_init(bd_t *bis)
 334 {
 335         int ret;
 336
 337         setup_iomux_enet();
 338
 339         ret = cpu_eth_init(bis);
 340         if (ret)
 341                 printf("FEC MXC: %s:failed\n", __func__);
 342
 343         return 0;
 344 }
 345
 346 static void setup_buttons(void)
 347 {
 348         imx_iomux_v3_setup_multiple_pads(button_pads,
 349                                          ARRAY_SIZE(button_pads));
 350 }
 351
 352 #ifdef CONFIG_CMD_SATA
 353
 354 int setup_sata(void)
 355 {
 356         struct iomuxc_base_regs *const iomuxc_regs
 357                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
 358         int ret = enable_sata_clock();
 359         if (ret)
 360                 return ret;
 361
 362         clrsetbits_le32(&iomuxc_regs->gpr[13],
 363                         IOMUXC_GPR13_SATA_MASK,
 364                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 365                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 366                         |IOMUXC_GPR13_SATA_SPEED_3G
 367                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 368                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 369                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
 370                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
 371                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
 372                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 373
 374         return 0;
 375 }
 376 #endif
 377
 378 int board_early_init_f(void)
 379 {
 380         setup_iomux_uart();
 381         setup_buttons();
 382
 383         return 0;
 384 }
 385
 386 int board_init(void)
 387 {
 388        /* address of boot parameters */
 389        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 390
 391 #ifdef CONFIG_MXC_SPI
 392         setup_spi();
 393 #endif
 394         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 395         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 396         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 397
 398 #ifdef CONFIG_CMD_SATA
 399         setup_sata();
 400 #endif
 401
 402        return 0;
 403 }
 404
 405 int checkboard(void)
 406 {
 407        puts("Board: MX6Q-Sabre Lite\n");
 408
 409        return 0;
 410 }
 411
 412 struct button_key {
 413         char const      *name;
 414         unsigned        gpnum;
 415         char            ident;
 416 };
 417
 418 static struct button_key const buttons[] = {
 419         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 420         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 421         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 422         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 423         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 424         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 425 };
 426
 427 /*
 428  * generate a null-terminated string containing the buttons pressed
 429  * returns number of keys pressed
 430  */
 431 static int read_keys(char *buf)
 432 {
 433         int i, numpressed = 0;
 434         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 435                 if (!gpio_get_value(buttons[i].gpnum))
 436                         buf[numpressed++] = buttons[i].ident;
 437         }
 438         buf[numpressed] = '\0';
 439         return numpressed;
 440 }
 441
 442 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 443 {
 444         char envvalue[ARRAY_SIZE(buttons)+1];
 445         int numpressed = read_keys(envvalue);
 446         setenv("keybd", envvalue);
 447         return numpressed == 0;
 448 }
 449
 450 U_BOOT_CMD(
 451         kbd, 1, 1, do_kbd,
 452         "Tests for keypresses, sets 'keybd' environment variable",
 453         "Returns 0 (true) to shell if key is pressed."
 454 );
 455
 456 #ifdef CONFIG_PREBOOT
 457 static char const kbd_magic_prefix[] = "key_magic";
 458 static char const kbd_command_prefix[] = "key_cmd";
 459
 460 static void preboot_keys(void)
 461 {
 462         int numpressed;
 463         char keypress[ARRAY_SIZE(buttons)+1];
 464         numpressed = read_keys(keypress);
 465         if (numpressed) {
 466                 char *kbd_magic_keys = getenv("magic_keys");
 467                 char *suffix;
 468                 /*
 469                  * loop over all magic keys
 470                  */
 471                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 472                         char *keys;
 473                         char magic[sizeof(kbd_magic_prefix) + 1];
 474                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 475                         keys = getenv(magic);
 476                         if (keys) {
 477                                 if (!strcmp(keys, keypress))
 478                                         break;
 479                         }
 480                 }
 481                 if (*suffix) {
 482                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 483                         char *cmd;
 484                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 485                         cmd = getenv(cmd_name);
 486                         if (cmd) {
 487                                 setenv("preboot", cmd);
 488                                 return;
 489                         }
 490                 }
 491         }
 492 }
 493 #endif
 494
 495 #ifdef CONFIG_CMD_BMODE
 496 static const struct boot_mode board_boot_modes[] = {
 497         /* 4 bit bus width */
 498         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 499         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 500         {NULL,          0},
 501 };
 502 #endif
 503
 504 int misc_init_r(void)
 505 {
 506 #ifdef CONFIG_PREBOOT
 507         preboot_keys();
 508 #endif
 509
 510 #ifdef CONFIG_CMD_BMODE
 511         add_board_boot_modes(board_boot_modes);
 512 #endif
 513         return 0;
 514 }