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[people/ms/u-boot.git] / board / freescale / mx6slevk / mx6slevk.c
1 /*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <asm/arch/clock.h>
10 #include <asm/arch/iomux.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-ddr.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h>
17 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <asm/imx-common/spi.h>
20 #include <asm/io.h>
21 #include <linux/sizes.h>
22 #include <common.h>
23 #include <fsl_esdhc.h>
24 #include <i2c.h>
25 #include <mmc.h>
26 #include <netdev.h>
27 #include <power/pmic.h>
28 #include <power/pfuze100_pmic.h>
29 #include "../common/pfuze.h"
30 #include <usb.h>
31 #include <usb/ehci-fsl.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42
43 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
45 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
46
47 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
49
50 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
51 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
52 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
53 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
54
55 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
57 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
58 PAD_CTL_SRE_FAST)
59
60 #define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
61
62 int dram_init(void)
63 {
64 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
65
66 return 0;
67 }
68
69 static iomux_v3_cfg_t const uart1_pads[] = {
70 MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
71 MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
72 };
73
74 static iomux_v3_cfg_t const usdhc1_pads[] = {
75 /* 8 bit SD */
76 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84 MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86
87 /*CD pin*/
88 MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
89 };
90
91 static iomux_v3_cfg_t const usdhc2_pads[] = {
92 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98
99 /*CD pin*/
100 MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
101 };
102
103 static iomux_v3_cfg_t const usdhc3_pads[] = {
104 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110
111 /*CD pin*/
112 MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
113 };
114
115 static iomux_v3_cfg_t const fec_pads[] = {
116 MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
126 MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
127 };
128
129 #ifdef CONFIG_MXC_SPI
130 static iomux_v3_cfg_t ecspi1_pads[] = {
131 MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
132 MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
133 MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
134 MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
135 };
136
137 int board_spi_cs_gpio(unsigned bus, unsigned cs)
138 {
139 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
140 }
141
142 static void setup_spi(void)
143 {
144 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
145 }
146 #endif
147
148 static void setup_iomux_uart(void)
149 {
150 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
151 }
152
153 static void setup_iomux_fec(void)
154 {
155 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
156
157 /* Reset LAN8720 PHY */
158 gpio_direction_output(ETH_PHY_RESET , 0);
159 udelay(25000);
160 gpio_set_value(ETH_PHY_RESET, 1);
161 }
162
163 #define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
164 #define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
165 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
166
167 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
168 {USDHC1_BASE_ADDR},
169 {USDHC2_BASE_ADDR, 0, 4},
170 {USDHC3_BASE_ADDR, 0, 4},
171 };
172
173 int board_mmc_get_env_dev(int devno)
174 {
175 return devno;
176 }
177
178 int board_mmc_getcd(struct mmc *mmc)
179 {
180 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
181 int ret = 0;
182
183 switch (cfg->esdhc_base) {
184 case USDHC1_BASE_ADDR:
185 ret = !gpio_get_value(USDHC1_CD_GPIO);
186 break;
187 case USDHC2_BASE_ADDR:
188 ret = !gpio_get_value(USDHC2_CD_GPIO);
189 break;
190 case USDHC3_BASE_ADDR:
191 ret = !gpio_get_value(USDHC3_CD_GPIO);
192 break;
193 }
194
195 return ret;
196 }
197
198 int board_mmc_init(bd_t *bis)
199 {
200 #ifndef CONFIG_SPL_BUILD
201 int i, ret;
202
203 /*
204 * According to the board_mmc_init() the following map is done:
205 * (U-boot device node) (Physical Port)
206 * mmc0 USDHC1
207 * mmc1 USDHC2
208 * mmc2 USDHC3
209 */
210 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
211 switch (i) {
212 case 0:
213 imx_iomux_v3_setup_multiple_pads(
214 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
215 gpio_direction_input(USDHC1_CD_GPIO);
216 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
217 break;
218 case 1:
219 imx_iomux_v3_setup_multiple_pads(
220 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
221 gpio_direction_input(USDHC2_CD_GPIO);
222 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
223 break;
224 case 2:
225 imx_iomux_v3_setup_multiple_pads(
226 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
227 gpio_direction_input(USDHC3_CD_GPIO);
228 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
229 break;
230 default:
231 printf("Warning: you configured more USDHC controllers"
232 "(%d) than supported by the board\n", i + 1);
233 return -EINVAL;
234 }
235
236 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
237 if (ret) {
238 printf("Warning: failed to initialize "
239 "mmc dev %d\n", i);
240 return ret;
241 }
242 }
243
244 return 0;
245 #else
246 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
247 u32 val;
248 u32 port;
249
250 val = readl(&src_regs->sbmr1);
251
252 /* Boot from USDHC */
253 port = (val >> 11) & 0x3;
254 switch (port) {
255 case 0:
256 imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
257 ARRAY_SIZE(usdhc1_pads));
258 gpio_direction_input(USDHC1_CD_GPIO);
259 usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
260 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
261 break;
262 case 1:
263 imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
264 ARRAY_SIZE(usdhc2_pads));
265 gpio_direction_input(USDHC2_CD_GPIO);
266 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
267 usdhc_cfg[0].max_bus_width = 4;
268 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
269 break;
270 case 2:
271 imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
272 ARRAY_SIZE(usdhc3_pads));
273 gpio_direction_input(USDHC3_CD_GPIO);
274 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
275 usdhc_cfg[0].max_bus_width = 4;
276 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
277 break;
278 }
279
280 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
281 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
282 #endif
283 }
284
285 #ifdef CONFIG_SYS_I2C_MXC
286 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
287 /* I2C1 for PMIC */
288 struct i2c_pads_info i2c_pad_info1 = {
289 .sda = {
290 .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
291 .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
292 .gp = IMX_GPIO_NR(3, 13),
293 },
294 .scl = {
295 .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
296 .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
297 .gp = IMX_GPIO_NR(3, 12),
298 },
299 };
300
301 int power_init_board(void)
302 {
303 struct pmic *p;
304
305 p = pfuze_common_init(I2C_PMIC);
306 if (!p)
307 return -ENODEV;
308
309 return pfuze_mode_init(p, APS_PFM);
310 }
311 #endif
312
313 #ifdef CONFIG_FEC_MXC
314 int board_eth_init(bd_t *bis)
315 {
316 setup_iomux_fec();
317
318 return cpu_eth_init(bis);
319 }
320
321 static int setup_fec(void)
322 {
323 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
324
325 /* clear gpr1[14], gpr1[18:17] to select anatop clock */
326 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
327
328 return enable_fec_anatop_clock(0, ENET_50MHZ);
329 }
330 #endif
331
332 #ifdef CONFIG_USB_EHCI_MX6
333 #define USB_OTHERREGS_OFFSET 0x800
334 #define UCTRL_PWR_POL (1 << 9)
335
336 static iomux_v3_cfg_t const usb_otg_pads[] = {
337 /* OTG1 */
338 MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
339 MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
340 /* OTG2 */
341 MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
342 };
343
344 static void setup_usb(void)
345 {
346 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
347 ARRAY_SIZE(usb_otg_pads));
348 }
349
350 int board_usb_phy_mode(int port)
351 {
352 if (port == 1)
353 return USB_INIT_HOST;
354 else
355 return usb_phy_mode(port);
356 }
357
358 int board_ehci_hcd_init(int port)
359 {
360 u32 *usbnc_usb_ctrl;
361
362 if (port > 1)
363 return -EINVAL;
364
365 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
366 port * 4);
367
368 /* Set Power polarity */
369 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
370
371 return 0;
372 }
373 #endif
374
375 int board_early_init_f(void)
376 {
377 setup_iomux_uart();
378 #ifdef CONFIG_MXC_SPI
379 setup_spi();
380 #endif
381 return 0;
382 }
383
384 int board_init(void)
385 {
386 /* address of boot parameters */
387 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
388
389 #ifdef CONFIG_SYS_I2C_MXC
390 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
391 #endif
392
393 #ifdef CONFIG_FEC_MXC
394 setup_fec();
395 #endif
396
397 #ifdef CONFIG_USB_EHCI_MX6
398 setup_usb();
399 #endif
400
401 return 0;
402 }
403
404 int checkboard(void)
405 {
406 puts("Board: MX6SLEVK\n");
407
408 return 0;
409 }
410
411 #ifdef CONFIG_SPL_BUILD
412 #include <spl.h>
413 #include <libfdt.h>
414
415 const struct mx6sl_iomux_ddr_regs mx6_ddr_ioregs = {
416 .dram_sdqs0 = 0x00003030,
417 .dram_sdqs1 = 0x00003030,
418 .dram_sdqs2 = 0x00003030,
419 .dram_sdqs3 = 0x00003030,
420 .dram_dqm0 = 0x00000030,
421 .dram_dqm1 = 0x00000030,
422 .dram_dqm2 = 0x00000030,
423 .dram_dqm3 = 0x00000030,
424 .dram_cas = 0x00000030,
425 .dram_ras = 0x00000030,
426 .dram_sdclk_0 = 0x00000028,
427 .dram_reset = 0x00000030,
428 .dram_sdba2 = 0x00000000,
429 .dram_odt0 = 0x00000008,
430 .dram_odt1 = 0x00000008,
431 };
432
433 const struct mx6sl_iomux_grp_regs mx6_grp_ioregs = {
434 .grp_b0ds = 0x00000030,
435 .grp_b1ds = 0x00000030,
436 .grp_b2ds = 0x00000030,
437 .grp_b3ds = 0x00000030,
438 .grp_addds = 0x00000030,
439 .grp_ctlds = 0x00000030,
440 .grp_ddrmode_ctl = 0x00020000,
441 .grp_ddrpke = 0x00000000,
442 .grp_ddrmode = 0x00020000,
443 .grp_ddr_type = 0x00080000,
444 };
445
446 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
447 .p0_mpdgctrl0 = 0x20000000,
448 .p0_mpdgctrl1 = 0x00000000,
449 .p0_mprddlctl = 0x4241444a,
450 .p0_mpwrdlctl = 0x3030312b,
451 .mpzqlp2ctl = 0x1b4700c7,
452 };
453
454 static struct mx6_lpddr2_cfg mem_ddr = {
455 .mem_speed = 800,
456 .density = 4,
457 .width = 32,
458 .banks = 8,
459 .rowaddr = 14,
460 .coladdr = 10,
461 .trcd_lp = 2000,
462 .trppb_lp = 2000,
463 .trpab_lp = 2250,
464 .trasmin = 4200,
465 };
466
467 static void ccgr_init(void)
468 {
469 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
470
471 writel(0xFFFFFFFF, &ccm->CCGR0);
472 writel(0xFFFFFFFF, &ccm->CCGR1);
473 writel(0xFFFFFFFF, &ccm->CCGR2);
474 writel(0xFFFFFFFF, &ccm->CCGR3);
475 writel(0xFFFFFFFF, &ccm->CCGR4);
476 writel(0xFFFFFFFF, &ccm->CCGR5);
477 writel(0xFFFFFFFF, &ccm->CCGR6);
478
479 writel(0x00260324, &ccm->cbcmr);
480 }
481
482 static void spl_dram_init(void)
483 {
484 struct mx6_ddr_sysinfo sysinfo = {
485 .dsize = mem_ddr.width / 32,
486 .cs_density = 20,
487 .ncs = 2,
488 .cs1_mirror = 0,
489 .walat = 0,
490 .ralat = 2,
491 .mif3_mode = 3,
492 .bi_on = 1,
493 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
494 .rtt_nom = 0,
495 .sde_to_rst = 0, /* LPDDR2 does not need this field */
496 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
497 .ddr_type = DDR_TYPE_LPDDR2,
498 };
499 mx6sl_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
500 mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
501 }
502
503 void board_init_f(ulong dummy)
504 {
505 /* setup AIPS and disable watchdog */
506 arch_cpu_init();
507
508 ccgr_init();
509
510 /* iomux and setup of i2c */
511 board_early_init_f();
512
513 /* setup GP timer */
514 timer_init();
515
516 /* UART clocks enabled and gd valid - init serial console */
517 preloader_console_init();
518
519 /* DDR initialization */
520 spl_dram_init();
521
522 /* Clear the BSS. */
523 memset(__bss_start, 0, __bss_end - __bss_start);
524
525 /* load/boot image from boot device */
526 board_init_r(NULL, 0);
527 }
528 #endif
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