1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
5 * Author: Ye Li <ye.li@nxp.com>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/boot_mode.h>
20 #include <linux/sizes.h>
22 #include <fsl_esdhc_imx.h>
25 #include <power/pmic.h>
26 #include <power/pfuze100_pmic.h>
27 #include "../common/pfuze.h"
29 #include <usb/ehci-ci.h>
32 DECLARE_GLOBAL_DATA_PTR
;
34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
39 PAD_CTL_SPEED_HIGH | \
40 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
42 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
43 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
45 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
46 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
48 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
49 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
51 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
55 gd
->ram_size
= imx_ddr_size();
60 static iomux_v3_cfg_t
const uart1_pads
[] = {
61 MX6_PAD_GPIO1_IO04__UART1_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
62 MX6_PAD_GPIO1_IO05__UART1_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
65 static iomux_v3_cfg_t
const fec2_pads
[] = {
66 MX6_PAD_ENET1_MDC__ENET2_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
67 MX6_PAD_ENET1_MDIO__ENET2_MDIO
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
68 MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
69 MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
70 MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
71 MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
72 MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
73 MX6_PAD_RGMII2_RXC__ENET2_RX_CLK
| MUX_PAD_CTRL(ENET_RX_PAD_CTRL
),
74 MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
75 MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
76 MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
77 MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
78 MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
79 MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
82 static void setup_iomux_uart(void)
84 imx_iomux_v3_setup_multiple_pads(uart1_pads
, ARRAY_SIZE(uart1_pads
));
87 static int setup_fec(void)
89 struct iomuxc
*iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
91 /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
92 clrsetbits_le32(&iomuxc_regs
->gpr
[1], IOMUX_GPR1_FEC2_MASK
, 0);
94 return enable_fec_anatop_clock(1, ENET_125MHZ
);
97 int board_eth_init(bd_t
*bis
)
101 imx_iomux_v3_setup_multiple_pads(fec2_pads
, ARRAY_SIZE(fec2_pads
));
104 ret
= fecmxc_initialize_multi(bis
, 1,
105 CONFIG_FEC_MXC_PHYADDR
, IMX_FEC_BASE
);
107 printf("FEC%d MXC: %s:failed\n", 1, __func__
);
112 int board_phy_config(struct phy_device
*phydev
)
115 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
116 * Phy control debug reg 0
118 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x1f);
119 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x8);
121 /* rgmii tx clock delay enable */
122 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1d, 0x05);
123 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1e, 0x100);
125 if (phydev
->drv
->config
)
126 phydev
->drv
->config(phydev
);
131 int power_init_board(void)
135 u32 dev_id
, rev_id
, i
;
137 u32 offset
= PFUZE100_SW1CMODE
;
139 ret
= pmic_get("pfuze100", &dev
);
146 dev_id
= pmic_reg_read(dev
, PFUZE100_DEVICEID
);
147 rev_id
= pmic_reg_read(dev
, PFUZE100_REVID
);
148 printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id
, rev_id
);
151 /* Init mode to APS_PFM */
152 pmic_reg_write(dev
, PFUZE100_SW1ABMODE
, APS_PFM
);
154 for (i
= 0; i
< switch_num
- 1; i
++)
155 pmic_reg_write(dev
, offset
+ i
* SWITCH_SIZE
, APS_PFM
);
157 /* set SW1AB staby volatage 0.975V */
158 pmic_clrsetbits(dev
, PFUZE100_SW1ABSTBY
, 0x3f, 0x1b);
160 /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
161 pmic_clrsetbits(dev
, PFUZE100_SW1ABCONF
, 0xc0, 0x40);
163 /* set SW1C staby volatage 1.10V */
164 pmic_clrsetbits(dev
, PFUZE100_SW1CSTBY
, 0x3f, 0x20);
166 /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
167 pmic_clrsetbits(dev
, PFUZE100_SW1CCONF
, 0xc0, 0x40);
172 #ifdef CONFIG_USB_EHCI_MX6
173 #define USB_OTHERREGS_OFFSET 0x800
174 #define UCTRL_PWR_POL (1 << 9)
176 static iomux_v3_cfg_t
const usb_otg_pads
[] = {
178 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
),
179 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID
| MUX_PAD_CTRL(NO_PAD_CTRL
),
181 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR
| MUX_PAD_CTRL(NO_PAD_CTRL
)
184 static void setup_usb(void)
186 imx_iomux_v3_setup_multiple_pads(usb_otg_pads
,
187 ARRAY_SIZE(usb_otg_pads
));
190 int board_usb_phy_mode(int port
)
193 return USB_INIT_HOST
;
195 return usb_phy_mode(port
);
198 int board_ehci_hcd_init(int port
)
205 usbnc_usb_ctrl
= (u32
*)(USB_BASE_ADDR
+ USB_OTHERREGS_OFFSET
+
208 /* Set Power polarity */
209 setbits_le32(usbnc_usb_ctrl
, UCTRL_PWR_POL
);
215 int board_early_init_f(void)
222 #ifdef CONFIG_FSL_QSPI
223 int board_qspi_init(void)
232 #ifdef CONFIG_NAND_MXS
233 iomux_v3_cfg_t gpmi_pads
[] = {
234 MX6_PAD_NAND_CLE__RAWNAND_CLE
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
235 MX6_PAD_NAND_ALE__RAWNAND_ALE
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
236 MX6_PAD_NAND_WP_B__RAWNAND_WP_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
237 MX6_PAD_NAND_READY_B__RAWNAND_READY_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL0
),
238 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
239 MX6_PAD_NAND_RE_B__RAWNAND_RE_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
240 MX6_PAD_NAND_WE_B__RAWNAND_WE_B
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
241 MX6_PAD_NAND_DATA00__RAWNAND_DATA00
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
242 MX6_PAD_NAND_DATA01__RAWNAND_DATA01
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
243 MX6_PAD_NAND_DATA02__RAWNAND_DATA02
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
244 MX6_PAD_NAND_DATA03__RAWNAND_DATA03
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
245 MX6_PAD_NAND_DATA04__RAWNAND_DATA04
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
246 MX6_PAD_NAND_DATA05__RAWNAND_DATA05
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
247 MX6_PAD_NAND_DATA06__RAWNAND_DATA06
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
248 MX6_PAD_NAND_DATA07__RAWNAND_DATA07
| MUX_PAD_CTRL(GPMI_PAD_CTRL2
),
251 static void setup_gpmi_nand(void)
253 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
255 /* config gpmi nand iomux */
256 imx_iomux_v3_setup_multiple_pads(gpmi_pads
, ARRAY_SIZE(gpmi_pads
));
258 setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
259 MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
260 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
262 /* enable apbh clock gating */
263 setbits_le32(&mxc_ccm
->CCGR0
, MXC_CCM_CCGR0_APBHDMA_MASK
);
269 struct gpio_desc desc
;
272 /* Address of boot parameters */
273 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
275 ret
= dm_gpio_lookup_name("gpio@30_4", &desc
);
279 ret
= dm_gpio_request(&desc
, "cpu_per_rst_b");
282 /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
283 dm_gpio_set_dir_flags(&desc
, GPIOD_IS_OUT
);
285 dm_gpio_set_value(&desc
, 1);
287 ret
= dm_gpio_lookup_name("gpio@32_2", &desc
);
291 ret
= dm_gpio_request(&desc
, "steer_enet");
295 dm_gpio_set_dir_flags(&desc
, GPIOD_IS_OUT
);
297 /* Set steering signal to L for selecting B0 */
298 dm_gpio_set_value(&desc
, 0);
300 #ifdef CONFIG_USB_EHCI_MX6
304 #ifdef CONFIG_FSL_QSPI
308 #ifdef CONFIG_NAND_MXS
315 #ifdef CONFIG_CMD_BMODE
316 static const struct boot_mode board_boot_modes
[] = {
317 {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
318 {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
319 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
320 {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
325 int board_late_init(void)
327 #ifdef CONFIG_CMD_BMODE
328 add_board_boot_modes(board_boot_modes
);
336 puts("Board: MX6SX SABRE AUTO\n");