board/freescale/mx6sxsabresd/mx6sxsabresd.c

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/io.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <linux/sizes.h>
  20 #include <common.h>
  21 #include <fsl_esdhc.h>
  22 #include <mmc.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <netdev.h>
  26 #include <power/pmic.h>
  27 #include <power/pfuze100_pmic.h>
  28 #include "../common/pfuze.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  33         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  34         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  37         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  38         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  41         PAD_CTL_SPEED_HIGH   |                                   \
  42         PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
  43
  44 #define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
  45         PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
  46
  47 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
  48         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  49
  50 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  51         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  52
  53 int dram_init(void)
  54 {
  55         gd->ram_size = imx_ddr_size();
  56
  57         return 0;
  58 }
  59
  60 static iomux_v3_cfg_t const uart1_pads[] = {
  61         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  62         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63 };
  64
  65 static iomux_v3_cfg_t const fec1_pads[] = {
  66         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  69         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  70         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  71         MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  72         MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  73         MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  74         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80 };
  81
  82 static iomux_v3_cfg_t const peri_3v3_pads[] = {
  83         MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  84 };
  85
  86 static iomux_v3_cfg_t const phy_control_pads[] = {
  87         /* 25MHz Ethernet PHY Clock */
  88         MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  89
  90         /* ENET PHY Power */
  91         MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
  92
  93         /* AR8031 PHY Reset */
  94         MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  95 };
  96
  97 static void setup_iomux_uart(void)
  98 {
  99         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 100 }
 101
 102 static int setup_fec(void)
 103 {
 104         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 105         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 106         int reg, ret;
 107
 108         /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
 109         clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
 110
 111         ret = enable_fec_anatop_clock(0, ENET_125MHZ);
 112         if (ret)
 113                 return ret;
 114
 115         imx_iomux_v3_setup_multiple_pads(phy_control_pads,
 116                                          ARRAY_SIZE(phy_control_pads));
 117
 118         /* Enable the ENET power, active low */
 119         gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
 120         gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
 121
 122         /* Reset AR8031 PHY */
 123         gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
 124         gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
 125         mdelay(10);
 126         gpio_set_value(IMX_GPIO_NR(2, 7), 1);
 127
 128         reg = readl(&anatop->pll_enet);
 129         reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 130         writel(reg, &anatop->pll_enet);
 131
 132         return 0;
 133 }
 134
 135 int board_eth_init(bd_t *bis)
 136 {
 137         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 138         setup_fec();
 139
 140         return cpu_eth_init(bis);
 141 }
 142
 143 int power_init_board(void)
 144 {
 145         struct udevice *dev;
 146         unsigned int reg;
 147         int ret;
 148
 149         dev = pfuze_common_init();
 150         if (!dev)
 151                 return -ENODEV;
 152
 153         ret = pfuze_mode_init(dev, APS_PFM);
 154         if (ret < 0)
 155                 return ret;
 156
 157         /* Enable power of VGEN5 3V3, needed for SD3 */
 158         reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
 159         reg &= ~LDO_VOL_MASK;
 160         reg |= (LDOB_3_30V | (1 << LDO_EN));
 161         pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
 162
 163         return 0;
 164 }
 165
 166 int board_phy_config(struct phy_device *phydev)
 167 {
 168         /*
 169          * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
 170          * Phy control debug reg 0
 171          */
 172         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 173         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 174
 175         /* rgmii tx clock delay enable */
 176         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 177         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 178
 179         if (phydev->drv->config)
 180                 phydev->drv->config(phydev);
 181
 182         return 0;
 183 }
 184
 185 int board_early_init_f(void)
 186 {
 187         setup_iomux_uart();
 188
 189         /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
 190         imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
 191                                          ARRAY_SIZE(peri_3v3_pads));
 192
 193         return 0;
 194 }
 195
 196 int board_mmc_get_env_dev(int devno)
 197 {
 198         return devno;
 199 }
 200
 201 #ifdef CONFIG_FSL_QSPI
 202
 203 #define QSPI_PAD_CTRL1  \
 204         (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
 205          PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
 206
 207 static iomux_v3_cfg_t const quadspi_pads[] = {
 208         MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 209         MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1    | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 210         MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2      | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 211         MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3      | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 212         MX6_PAD_NAND_ALE__QSPI2_A_SS0_B         | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 213         MX6_PAD_NAND_CLE__QSPI2_A_SCLK          | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 214         MX6_PAD_NAND_DATA07__QSPI2_A_DQS        | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 215         MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 216         MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1     | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 217         MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 218         MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 219         MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B      | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 220         MX6_PAD_NAND_DATA02__QSPI2_B_SCLK       | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 221         MX6_PAD_NAND_DATA05__QSPI2_B_DQS        | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 222 };
 223
 224 int board_qspi_init(void)
 225 {
 226         /* Set the iomux */
 227         imx_iomux_v3_setup_multiple_pads(quadspi_pads,
 228                                          ARRAY_SIZE(quadspi_pads));
 229
 230         /* Set the clock */
 231         enable_qspi_clk(1);
 232
 233         return 0;
 234 }
 235 #endif
 236
 237 #ifdef CONFIG_VIDEO_MXS
 238 static iomux_v3_cfg_t const lcd_pads[] = {
 239         MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 240         MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
 241         MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 242         MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
 243         MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 244         MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 245         MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 246         MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 247         MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 248         MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 249         MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 250         MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 251         MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 252         MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 253         MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 254         MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 255         MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 256         MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 257         MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 258         MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 259         MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 260         MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 261         MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 262         MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 263         MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 264         MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 265         MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 266         MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 267         MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
 268
 269         /* Use GPIO for Brightness adjustment, duty cycle = period */
 270         MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
 271 };
 272
 273 static int setup_lcd(void)
 274 {
 275         enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
 276
 277         imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 278
 279         /* Reset the LCD */
 280         gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
 281         gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
 282         udelay(500);
 283         gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
 284
 285         /* Set Brightness to high */
 286         gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
 287         gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
 288
 289         return 0;
 290 }
 291 #endif
 292
 293 int board_init(void)
 294 {
 295         /* Address of boot parameters */
 296         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 297
 298         /* Active high for ncp692 */
 299         gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
 300         gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
 301
 302 #ifdef CONFIG_FSL_QSPI
 303         board_qspi_init();
 304 #endif
 305
 306 #ifdef CONFIG_VIDEO_MXS
 307         setup_lcd();
 308 #endif
 309
 310         return 0;
 311 }
 312
 313 static bool is_reva(void)
 314 {
 315         return (nxp_board_rev() == 1);
 316 }
 317
 318 int board_late_init(void)
 319 {
 320 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 321         if (is_reva())
 322                 env_set("board_rev", "REVA");
 323 #endif
 324         return 0;
 325 }
 326
 327 int checkboard(void)
 328 {
 329         printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
 330
 331         return 0;
 332 }
 333
 334 #ifdef CONFIG_SPL_BUILD
 335 #include <libfdt.h>
 336 #include <spl.h>
 337 #include <asm/arch/mx6-ddr.h>
 338
 339 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
 340         {USDHC2_BASE_ADDR, 0, 4},
 341         {USDHC3_BASE_ADDR},
 342         {USDHC4_BASE_ADDR},
 343 };
 344
 345 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 10)
 346 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
 347 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 21)
 348
 349 static iomux_v3_cfg_t const usdhc2_pads[] = {
 350         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 351         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 352         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 353         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 354         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 355         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 356 };
 357
 358 static iomux_v3_cfg_t const usdhc3_pads[] = {
 359         MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 360         MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 361         MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 362         MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 363         MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 364         MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 365         MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 366         MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 367         MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 368         MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 369
 370         /* CD pin */
 371         MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 372
 373         /* RST_B, used for power reset cycle */
 374         MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 375 };
 376
 377 static iomux_v3_cfg_t const usdhc4_pads[] = {
 378         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 379         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 380         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 381         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 382         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 383         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 384         MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 385 };
 386
 387 int board_mmc_init(bd_t *bis)
 388 {
 389         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
 390         u32 val;
 391         u32 port;
 392
 393         val = readl(&src_regs->sbmr1);
 394
 395         if ((val & 0xc0) != 0x40) {
 396                 printf("Not boot from USDHC!\n");
 397                 return -EINVAL;
 398         }
 399
 400         port = (val >> 11) & 0x3;
 401         printf("port %d\n", port);
 402         switch (port) {
 403         case 1:
 404                 imx_iomux_v3_setup_multiple_pads(
 405                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 406                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 407                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 408                 break;
 409         case 2:
 410                 imx_iomux_v3_setup_multiple_pads(
 411                         usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 412                 gpio_direction_input(USDHC3_CD_GPIO);
 413                 gpio_direction_output(USDHC3_PWR_GPIO, 1);
 414                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 415                 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
 416                 break;
 417         case 3:
 418                 imx_iomux_v3_setup_multiple_pads(
 419                         usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 420                 gpio_direction_input(USDHC4_CD_GPIO);
 421                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 422                 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 423                 break;
 424         }
 425
 426         gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 427         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 428 }
 429
 430 int board_mmc_getcd(struct mmc *mmc)
 431 {
 432         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 433         int ret = 0;
 434
 435         switch (cfg->esdhc_base) {
 436         case USDHC2_BASE_ADDR:
 437                 ret = 1; /* Assume uSDHC2 is always present */
 438                 break;
 439         case USDHC3_BASE_ADDR:
 440                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 441                 break;
 442         case USDHC4_BASE_ADDR:
 443                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 444                 break;
 445         }
 446
 447         return ret;
 448 }
 449
 450 const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
 451         .dram_dqm0 = 0x00000028,
 452         .dram_dqm1 = 0x00000028,
 453         .dram_dqm2 = 0x00000028,
 454         .dram_dqm3 = 0x00000028,
 455         .dram_ras = 0x00000020,
 456         .dram_cas = 0x00000020,
 457         .dram_odt0 = 0x00000020,
 458         .dram_odt1 = 0x00000020,
 459         .dram_sdba2 = 0x00000000,
 460         .dram_sdcke0 = 0x00003000,
 461         .dram_sdcke1 = 0x00003000,
 462         .dram_sdclk_0 = 0x00000030,
 463         .dram_sdqs0 = 0x00000028,
 464         .dram_sdqs1 = 0x00000028,
 465         .dram_sdqs2 = 0x00000028,
 466         .dram_sdqs3 = 0x00000028,
 467         .dram_reset = 0x00000020,
 468 };
 469
 470 const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
 471         .grp_addds = 0x00000020,
 472         .grp_ddrmode_ctl = 0x00020000,
 473         .grp_ddrpke = 0x00000000,
 474         .grp_ddrmode = 0x00020000,
 475         .grp_b0ds = 0x00000028,
 476         .grp_b1ds = 0x00000028,
 477         .grp_ctlds = 0x00000020,
 478         .grp_ddr_type = 0x000c0000,
 479         .grp_b2ds = 0x00000028,
 480         .grp_b3ds = 0x00000028,
 481 };
 482
 483 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 484         .p0_mpwldectrl0 = 0x00290025,
 485         .p0_mpwldectrl1 = 0x00220022,
 486         .p0_mpdgctrl0 = 0x41480144,
 487         .p0_mpdgctrl1 = 0x01340130,
 488         .p0_mprddlctl = 0x3C3E4244,
 489         .p0_mpwrdlctl = 0x34363638,
 490 };
 491
 492 static struct mx6_ddr3_cfg mem_ddr = {
 493         .mem_speed = 1600,
 494         .density = 4,
 495         .width = 32,
 496         .banks = 8,
 497         .rowaddr = 15,
 498         .coladdr = 10,
 499         .pagesz = 2,
 500         .trcd = 1375,
 501         .trcmin = 4875,
 502         .trasmin = 3500,
 503 };
 504
 505 static void ccgr_init(void)
 506 {
 507         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 508
 509         writel(0xFFFFFFFF, &ccm->CCGR0);
 510         writel(0xFFFFFFFF, &ccm->CCGR1);
 511         writel(0xFFFFFFFF, &ccm->CCGR2);
 512         writel(0xFFFFFFFF, &ccm->CCGR3);
 513         writel(0xFFFFFFFF, &ccm->CCGR4);
 514         writel(0xFFFFFFFF, &ccm->CCGR5);
 515         writel(0xFFFFFFFF, &ccm->CCGR6);
 516         writel(0xFFFFFFFF, &ccm->CCGR7);
 517 }
 518
 519 static void spl_dram_init(void)
 520 {
 521         struct mx6_ddr_sysinfo sysinfo = {
 522                 .dsize = mem_ddr.width/32,
 523                 .cs_density = 24,
 524                 .ncs = 1,
 525                 .cs1_mirror = 0,
 526                 .rtt_wr = 2,
 527                 .rtt_nom = 2,           /* RTT_Nom = RZQ/2 */
 528                 .walat = 1,             /* Write additional latency */
 529                 .ralat = 5,             /* Read additional latency */
 530                 .mif3_mode = 3,         /* Command prediction working mode */
 531                 .bi_on = 1,             /* Bank interleaving enabled */
 532                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 533                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 534                 .ddr_type = DDR_TYPE_DDR3,
 535                 .refsel = 1,    /* Refresh cycles at 32KHz */
 536                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 537         };
 538
 539         mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 540         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 541 }
 542
 543 void board_init_f(ulong dummy)
 544 {
 545         /* setup AIPS and disable watchdog */
 546         arch_cpu_init();
 547
 548         ccgr_init();
 549
 550         /* iomux and setup of i2c */
 551         board_early_init_f();
 552
 553         /* setup GP timer */
 554         timer_init();
 555
 556         /* UART clocks enabled and gd valid - init serial console */
 557         preloader_console_init();
 558
 559         /* DDR initialization */
 560         spl_dram_init();
 561
 562         /* Clear the BSS. */
 563         memset(__bss_start, 0, __bss_end - __bss_start);
 564
 565         /* load/boot image from boot device */
 566         board_init_r(NULL, 0);
 567 }
 568 #endif