2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clock.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6ul_pins.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/mxc_i2c.h>
20 #include <fsl_esdhc.h>
23 #include <linux/sizes.h>
26 #include <power/pmic.h>
27 #include <power/pfuze3000_pmic.h>
28 #include "../common/pfuze.h"
30 #include <usb/ehci-ci.h>
32 DECLARE_GLOBAL_DATA_PTR
;
34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
44 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
46 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
51 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 PAD_CTL_SPEED_HIGH | \
53 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
55 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
56 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
58 #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
59 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
61 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
63 #define IOX_SDI IMX_GPIO_NR(5, 10)
64 #define IOX_STCP IMX_GPIO_NR(5, 7)
65 #define IOX_SHCP IMX_GPIO_NR(5, 11)
66 #define IOX_OE IMX_GPIO_NR(5, 8)
68 static iomux_v3_cfg_t
const iox_pads
[] = {
70 MX6_PAD_BOOT_MODE0__GPIO5_IO10
| MUX_PAD_CTRL(NO_PAD_CTRL
),
72 MX6_PAD_BOOT_MODE1__GPIO5_IO11
| MUX_PAD_CTRL(NO_PAD_CTRL
),
74 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07
| MUX_PAD_CTRL(NO_PAD_CTRL
),
76 MX6_PAD_SNVS_TAMPER8__GPIO5_IO08
| MUX_PAD_CTRL(NO_PAD_CTRL
),
111 static enum qn_level seq
[3][2] = {
112 {0, 1}, {1, 1}, {0, 0}
115 static enum qn_func qn_output
[8] = {
116 qn_reset
, qn_reset
, qn_reset
, qn_enable
, qn_disable
, qn_reset
,
117 qn_disable
, qn_disable
120 static void iox74lv_init(void)
124 gpio_direction_output(IOX_OE
, 0);
126 for (i
= 7; i
>= 0; i
--) {
127 gpio_direction_output(IOX_SHCP
, 0);
128 gpio_direction_output(IOX_SDI
, seq
[qn_output
[i
]][0]);
130 gpio_direction_output(IOX_SHCP
, 1);
134 gpio_direction_output(IOX_STCP
, 0);
137 * shift register will be output to pins
139 gpio_direction_output(IOX_STCP
, 1);
141 for (i
= 7; i
>= 0; i
--) {
142 gpio_direction_output(IOX_SHCP
, 0);
143 gpio_direction_output(IOX_SDI
, seq
[qn_output
[i
]][1]);
145 gpio_direction_output(IOX_SHCP
, 1);
148 gpio_direction_output(IOX_STCP
, 0);
151 * shift register will be output to pins
153 gpio_direction_output(IOX_STCP
, 1);
156 #ifdef CONFIG_SYS_I2C_MXC
157 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
158 /* I2C1 for PMIC and EEPROM */
159 static struct i2c_pads_info i2c_pad_info1
= {
161 .i2c_mode
= MX6_PAD_UART4_TX_DATA__I2C1_SCL
| PC
,
162 .gpio_mode
= MX6_PAD_UART4_TX_DATA__GPIO1_IO28
| PC
,
163 .gp
= IMX_GPIO_NR(1, 28),
166 .i2c_mode
= MX6_PAD_UART4_RX_DATA__I2C1_SDA
| PC
,
167 .gpio_mode
= MX6_PAD_UART4_RX_DATA__GPIO1_IO29
| PC
,
168 .gp
= IMX_GPIO_NR(1, 29),
174 int power_init_board(void)
176 if (is_mx6ul_9x9_evk()) {
179 unsigned int reg
, rev_id
;
181 ret
= power_pfuze3000_init(I2C_PMIC
);
185 pfuze
= pmic_get("PFUZE3000");
186 ret
= pmic_probe(pfuze
);
190 pmic_reg_read(pfuze
, PFUZE3000_DEVICEID
, ®
);
191 pmic_reg_read(pfuze
, PFUZE3000_REVID
, &rev_id
);
192 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n",
195 /* disable Low Power Mode during standby mode */
196 pmic_reg_write(pfuze
, PFUZE3000_LDOGCTL
, 0x1);
198 /* SW1B step ramp up time from 2us to 4us/25mV */
200 pmic_reg_write(pfuze
, PFUZE3000_SW1BCONF
, reg
);
202 /* SW1B mode to APS/PFM */
204 pmic_reg_write(pfuze
, PFUZE3000_SW1BMODE
, reg
);
206 /* SW1B standby voltage set to 0.975V */
208 pmic_reg_write(pfuze
, PFUZE3000_SW1BSTBY
, reg
);
218 gd
->ram_size
= imx_ddr_size();
223 static iomux_v3_cfg_t
const uart1_pads
[] = {
224 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
225 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX
| MUX_PAD_CTRL(UART_PAD_CTRL
),
228 static iomux_v3_cfg_t
const usdhc1_pads
[] = {
229 MX6_PAD_SD1_CLK__USDHC1_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
230 MX6_PAD_SD1_CMD__USDHC1_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
231 MX6_PAD_SD1_DATA0__USDHC1_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
232 MX6_PAD_SD1_DATA1__USDHC1_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
233 MX6_PAD_SD1_DATA2__USDHC1_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
234 MX6_PAD_SD1_DATA3__USDHC1_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
237 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
239 MX6_PAD_UART1_RTS_B__GPIO1_IO19
| MUX_PAD_CTRL(NO_PAD_CTRL
),
241 MX6_PAD_GPIO1_IO09__GPIO1_IO09
| MUX_PAD_CTRL(NO_PAD_CTRL
),
245 * mx6ul_14x14_evk board default supports sd card. If want to use
246 * EMMC, need to do board rework for sd2.
247 * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
248 * emmc, need to define this macro.
250 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
251 static iomux_v3_cfg_t
const usdhc2_emmc_pads
[] = {
252 MX6_PAD_NAND_RE_B__USDHC2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
253 MX6_PAD_NAND_WE_B__USDHC2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
254 MX6_PAD_NAND_DATA00__USDHC2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
255 MX6_PAD_NAND_DATA01__USDHC2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
256 MX6_PAD_NAND_DATA02__USDHC2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
257 MX6_PAD_NAND_DATA03__USDHC2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
258 MX6_PAD_NAND_DATA04__USDHC2_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
259 MX6_PAD_NAND_DATA05__USDHC2_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
260 MX6_PAD_NAND_DATA06__USDHC2_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
261 MX6_PAD_NAND_DATA07__USDHC2_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
266 MX6_PAD_NAND_ALE__GPIO4_IO10
| MUX_PAD_CTRL(NO_PAD_CTRL
),
269 static iomux_v3_cfg_t
const usdhc2_pads
[] = {
270 MX6_PAD_NAND_RE_B__USDHC2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
271 MX6_PAD_NAND_WE_B__USDHC2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
272 MX6_PAD_NAND_DATA00__USDHC2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
273 MX6_PAD_NAND_DATA01__USDHC2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
274 MX6_PAD_NAND_DATA02__USDHC2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
275 MX6_PAD_NAND_DATA03__USDHC2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
279 * The evk board uses DAT3 to detect CD card plugin,
280 * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
282 static iomux_v3_cfg_t
const usdhc2_cd_pad
=
283 MX6_PAD_NAND_DATA03__GPIO4_IO05
| MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL
);
285 static iomux_v3_cfg_t
const usdhc2_dat3_pad
=
286 MX6_PAD_NAND_DATA03__USDHC2_DATA3
|
287 MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL
);
290 static void setup_iomux_uart(void)
292 imx_iomux_v3_setup_multiple_pads(uart1_pads
, ARRAY_SIZE(uart1_pads
));
295 #ifdef CONFIG_FSL_QSPI
297 #define QSPI_PAD_CTRL1 \
298 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
299 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
301 static iomux_v3_cfg_t
const quadspi_pads
[] = {
302 MX6_PAD_NAND_WP_B__QSPI_A_SCLK
| MUX_PAD_CTRL(QSPI_PAD_CTRL1
),
303 MX6_PAD_NAND_READY_B__QSPI_A_DATA00
| MUX_PAD_CTRL(QSPI_PAD_CTRL1
),
304 MX6_PAD_NAND_CE0_B__QSPI_A_DATA01
| MUX_PAD_CTRL(QSPI_PAD_CTRL1
),
305 MX6_PAD_NAND_CE1_B__QSPI_A_DATA02
| MUX_PAD_CTRL(QSPI_PAD_CTRL1
),
306 MX6_PAD_NAND_CLE__QSPI_A_DATA03
| MUX_PAD_CTRL(QSPI_PAD_CTRL1
),
307 MX6_PAD_NAND_DQS__QSPI_A_SS0_B
| MUX_PAD_CTRL(QSPI_PAD_CTRL1
),
310 static int board_qspi_init(void)
313 imx_iomux_v3_setup_multiple_pads(quadspi_pads
,
314 ARRAY_SIZE(quadspi_pads
));
322 #ifdef CONFIG_FSL_ESDHC
323 static struct fsl_esdhc_cfg usdhc_cfg
[2] = {
324 {USDHC1_BASE_ADDR
, 0, 4},
325 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
326 {USDHC2_BASE_ADDR
, 0, 8},
328 {USDHC2_BASE_ADDR
, 0, 4},
332 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
333 #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
334 #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
335 #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
337 int board_mmc_getcd(struct mmc
*mmc
)
339 struct fsl_esdhc_cfg
*cfg
= (struct fsl_esdhc_cfg
*)mmc
->priv
;
342 switch (cfg
->esdhc_base
) {
343 case USDHC1_BASE_ADDR
:
344 ret
= !gpio_get_value(USDHC1_CD_GPIO
);
346 case USDHC2_BASE_ADDR
:
347 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
350 imx_iomux_v3_setup_pad(usdhc2_cd_pad
);
351 gpio_direction_input(USDHC2_CD_GPIO
);
354 * Since it is the DAT3 pin, this pin is pulled to
355 * low voltage if no card
357 ret
= gpio_get_value(USDHC2_CD_GPIO
);
359 imx_iomux_v3_setup_pad(usdhc2_dat3_pad
);
367 int board_mmc_init(bd_t
*bis
)
369 #ifdef CONFIG_SPL_BUILD
370 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
371 imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads
,
372 ARRAY_SIZE(usdhc2_emmc_pads
));
374 imx_iomux_v3_setup_multiple_pads(usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
376 gpio_direction_output(USDHC2_PWR_GPIO
, 0);
378 gpio_direction_output(USDHC2_PWR_GPIO
, 1);
379 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
380 return fsl_esdhc_initialize(bis
, &usdhc_cfg
[1]);
385 * According to the board_mmc_init() the following map is done:
386 * (U-Boot device node) (Physical Port)
390 for (i
= 0; i
< CONFIG_SYS_FSL_USDHC_NUM
; i
++) {
393 imx_iomux_v3_setup_multiple_pads(
394 usdhc1_pads
, ARRAY_SIZE(usdhc1_pads
));
395 gpio_direction_input(USDHC1_CD_GPIO
);
396 usdhc_cfg
[0].sdhc_clk
= mxc_get_clock(MXC_ESDHC_CLK
);
398 gpio_direction_output(USDHC1_PWR_GPIO
, 0);
400 gpio_direction_output(USDHC1_PWR_GPIO
, 1);
403 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
404 imx_iomux_v3_setup_multiple_pads(
405 usdhc2_emmc_pads
, ARRAY_SIZE(usdhc2_emmc_pads
));
407 imx_iomux_v3_setup_multiple_pads(
408 usdhc2_pads
, ARRAY_SIZE(usdhc2_pads
));
410 gpio_direction_output(USDHC2_PWR_GPIO
, 0);
412 gpio_direction_output(USDHC2_PWR_GPIO
, 1);
413 usdhc_cfg
[1].sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
416 printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i
+ 1);
420 ret
= fsl_esdhc_initialize(bis
, &usdhc_cfg
[i
]);
422 printf("Warning: failed to initialize mmc dev %d\n", i
);
431 #ifdef CONFIG_USB_EHCI_MX6
432 #define USB_OTHERREGS_OFFSET 0x800
433 #define UCTRL_PWR_POL (1 << 9)
435 static iomux_v3_cfg_t
const usb_otg_pads
[] = {
436 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID
| MUX_PAD_CTRL(NO_PAD_CTRL
),
439 /* At default the 3v3 enables the MIC2026 for VBUS power */
440 static void setup_usb(void)
442 imx_iomux_v3_setup_multiple_pads(usb_otg_pads
,
443 ARRAY_SIZE(usb_otg_pads
));
446 int board_usb_phy_mode(int port
)
449 return USB_INIT_HOST
;
451 return usb_phy_mode(port
);
454 int board_ehci_hcd_init(int port
)
461 usbnc_usb_ctrl
= (u32
*)(USB_BASE_ADDR
+ USB_OTHERREGS_OFFSET
+
464 /* Set Power polarity */
465 setbits_le32(usbnc_usb_ctrl
, UCTRL_PWR_POL
);
471 #ifdef CONFIG_FEC_MXC
473 * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
474 * be used for ENET1 or ENET2, cannot be used for both.
476 static iomux_v3_cfg_t
const fec1_pads
[] = {
477 MX6_PAD_GPIO1_IO06__ENET1_MDIO
| MUX_PAD_CTRL(MDIO_PAD_CTRL
),
478 MX6_PAD_GPIO1_IO07__ENET1_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
479 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
480 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
481 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
482 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1
| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL
),
483 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
484 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
485 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
486 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
489 static iomux_v3_cfg_t
const fec2_pads
[] = {
490 MX6_PAD_GPIO1_IO06__ENET2_MDIO
| MUX_PAD_CTRL(MDIO_PAD_CTRL
),
491 MX6_PAD_GPIO1_IO07__ENET2_MDC
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
493 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
494 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
495 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2
| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL
),
496 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
498 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
499 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
500 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
501 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER
| MUX_PAD_CTRL(ENET_PAD_CTRL
),
504 static void setup_iomux_fec(int fec_id
)
507 imx_iomux_v3_setup_multiple_pads(fec1_pads
,
508 ARRAY_SIZE(fec1_pads
));
510 imx_iomux_v3_setup_multiple_pads(fec2_pads
,
511 ARRAY_SIZE(fec2_pads
));
514 int board_eth_init(bd_t
*bis
)
516 setup_iomux_fec(CONFIG_FEC_ENET_DEV
);
518 return fecmxc_initialize_multi(bis
, CONFIG_FEC_ENET_DEV
,
519 CONFIG_FEC_MXC_PHYADDR
, IMX_FEC_BASE
);
522 static int setup_fec(int fec_id
)
524 struct iomuxc
*const iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
529 * Use 50M anatop loopback REF_CLK1 for ENET1,
530 * clear gpr1[13], set gpr1[17].
532 clrsetbits_le32(&iomuxc_regs
->gpr
[1], IOMUX_GPR1_FEC1_MASK
,
533 IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK
);
536 * Use 50M anatop loopback REF_CLK2 for ENET2,
537 * clear gpr1[14], set gpr1[18].
539 clrsetbits_le32(&iomuxc_regs
->gpr
[1], IOMUX_GPR1_FEC2_MASK
,
540 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK
);
543 ret
= enable_fec_anatop_clock(fec_id
, ENET_50MHZ
);
552 int board_phy_config(struct phy_device
*phydev
)
554 phy_write(phydev
, MDIO_DEVAD_NONE
, 0x1f, 0x8190);
556 if (phydev
->drv
->config
)
557 phydev
->drv
->config(phydev
);
563 #ifdef CONFIG_VIDEO_MXS
564 static iomux_v3_cfg_t
const lcd_pads
[] = {
565 MX6_PAD_LCD_CLK__LCDIF_CLK
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
566 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
567 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
568 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
569 MX6_PAD_LCD_DATA00__LCDIF_DATA00
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
570 MX6_PAD_LCD_DATA01__LCDIF_DATA01
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
571 MX6_PAD_LCD_DATA02__LCDIF_DATA02
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
572 MX6_PAD_LCD_DATA03__LCDIF_DATA03
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
573 MX6_PAD_LCD_DATA04__LCDIF_DATA04
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
574 MX6_PAD_LCD_DATA05__LCDIF_DATA05
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
575 MX6_PAD_LCD_DATA06__LCDIF_DATA06
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
576 MX6_PAD_LCD_DATA07__LCDIF_DATA07
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
577 MX6_PAD_LCD_DATA08__LCDIF_DATA08
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
578 MX6_PAD_LCD_DATA09__LCDIF_DATA09
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
579 MX6_PAD_LCD_DATA10__LCDIF_DATA10
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
580 MX6_PAD_LCD_DATA11__LCDIF_DATA11
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
581 MX6_PAD_LCD_DATA12__LCDIF_DATA12
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
582 MX6_PAD_LCD_DATA13__LCDIF_DATA13
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
583 MX6_PAD_LCD_DATA14__LCDIF_DATA14
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
584 MX6_PAD_LCD_DATA15__LCDIF_DATA15
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
585 MX6_PAD_LCD_DATA16__LCDIF_DATA16
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
586 MX6_PAD_LCD_DATA17__LCDIF_DATA17
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
587 MX6_PAD_LCD_DATA18__LCDIF_DATA18
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
588 MX6_PAD_LCD_DATA19__LCDIF_DATA19
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
589 MX6_PAD_LCD_DATA20__LCDIF_DATA20
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
590 MX6_PAD_LCD_DATA21__LCDIF_DATA21
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
591 MX6_PAD_LCD_DATA22__LCDIF_DATA22
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
592 MX6_PAD_LCD_DATA23__LCDIF_DATA23
| MUX_PAD_CTRL(LCD_PAD_CTRL
),
595 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09
| MUX_PAD_CTRL(NO_PAD_CTRL
),
597 /* Use GPIO for Brightness adjustment, duty cycle = period. */
598 MX6_PAD_GPIO1_IO08__GPIO1_IO08
| MUX_PAD_CTRL(NO_PAD_CTRL
),
601 static int setup_lcd(void)
603 enable_lcdif_clock(LCDIF1_BASE_ADDR
, 1);
605 imx_iomux_v3_setup_multiple_pads(lcd_pads
, ARRAY_SIZE(lcd_pads
));
608 gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
610 gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
612 /* Set Brightness to high */
613 gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
619 int board_early_init_f(void)
628 /* Address of boot parameters */
629 gd
->bd
->bi_boot_params
= PHYS_SDRAM
+ 0x100;
631 imx_iomux_v3_setup_multiple_pads(iox_pads
, ARRAY_SIZE(iox_pads
));
635 #ifdef CONFIG_SYS_I2C_MXC
636 setup_i2c(0, CONFIG_SYS_I2C_SPEED
, 0x7f, &i2c_pad_info1
);
639 #ifdef CONFIG_FEC_MXC
640 setup_fec(CONFIG_FEC_ENET_DEV
);
643 #ifdef CONFIG_USB_EHCI_MX6
647 #ifdef CONFIG_FSL_QSPI
651 #ifdef CONFIG_VIDEO_MXS
658 #ifdef CONFIG_CMD_BMODE
659 static const struct boot_mode board_boot_modes
[] = {
660 /* 4 bit bus width */
661 {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
662 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
663 {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
668 int board_late_init(void)
670 #ifdef CONFIG_CMD_BMODE
671 add_board_boot_modes(board_boot_modes
);
674 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
675 setenv("board_name", "EVK");
677 if (is_mx6ul_9x9_evk())
678 setenv("board_rev", "9X9");
680 setenv("board_rev", "14X14");
688 if (is_mx6ul_9x9_evk())
689 puts("Board: MX6UL 9x9 EVK\n");
691 puts("Board: MX6UL 14x14 EVK\n");
696 #ifdef CONFIG_SPL_BUILD
699 #include <asm/arch/mx6-ddr.h>
702 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs
= {
703 .grp_addds
= 0x00000030,
704 .grp_ddrmode_ctl
= 0x00020000,
705 .grp_b0ds
= 0x00000030,
706 .grp_ctlds
= 0x00000030,
707 .grp_b1ds
= 0x00000030,
708 .grp_ddrpke
= 0x00000000,
709 .grp_ddrmode
= 0x00020000,
710 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
711 .grp_ddr_type
= 0x00080000,
713 .grp_ddr_type
= 0x000c0000,
717 #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
718 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs
= {
719 .dram_dqm0
= 0x00000030,
720 .dram_dqm1
= 0x00000030,
721 .dram_ras
= 0x00000030,
722 .dram_cas
= 0x00000030,
723 .dram_odt0
= 0x00000000,
724 .dram_odt1
= 0x00000000,
725 .dram_sdba2
= 0x00000000,
726 .dram_sdclk_0
= 0x00000030,
727 .dram_sdqs0
= 0x00003030,
728 .dram_sdqs1
= 0x00003030,
729 .dram_reset
= 0x00000030,
732 static struct mx6_mmdc_calibration mx6_mmcd_calib
= {
733 .p0_mpwldectrl0
= 0x00000000,
734 .p0_mpdgctrl0
= 0x20000000,
735 .p0_mprddlctl
= 0x4040484f,
736 .p0_mpwrdlctl
= 0x40405247,
737 .mpzqlp2ctl
= 0x1b4700c7,
740 static struct mx6_lpddr2_cfg mem_ddr
= {
753 struct mx6_ddr_sysinfo ddr_sysinfo
= {
762 .rtt_wr
= 0, /* LPDDR2 does not need rtt_wr rtt_nom */
764 .sde_to_rst
= 0, /* LPDDR2 does not need this field */
765 .rst_to_cke
= 0x10, /* JEDEC value for LPDDR2: 200us */
766 .ddr_type
= DDR_TYPE_LPDDR2
,
767 .refsel
= 0, /* Refresh cycles at 64KHz */
768 .refr
= 3, /* 4 refresh commands per refresh cycle */
772 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs
= {
773 .dram_dqm0
= 0x00000030,
774 .dram_dqm1
= 0x00000030,
775 .dram_ras
= 0x00000030,
776 .dram_cas
= 0x00000030,
777 .dram_odt0
= 0x00000030,
778 .dram_odt1
= 0x00000030,
779 .dram_sdba2
= 0x00000000,
780 .dram_sdclk_0
= 0x00000030,
781 .dram_sdqs0
= 0x00000030,
782 .dram_sdqs1
= 0x00000030,
783 .dram_reset
= 0x00000030,
786 static struct mx6_mmdc_calibration mx6_mmcd_calib
= {
787 .p0_mpwldectrl0
= 0x00000000,
788 .p0_mpdgctrl0
= 0x41570155,
789 .p0_mprddlctl
= 0x4040474A,
790 .p0_mpwrdlctl
= 0x40405550,
793 struct mx6_ddr_sysinfo ddr_sysinfo
= {
799 .rtt_nom
= 1, /* RTT_Nom = RZQ/2 */
800 .walat
= 0, /* Write additional latency */
801 .ralat
= 5, /* Read additional latency */
802 .mif3_mode
= 3, /* Command prediction working mode */
803 .bi_on
= 1, /* Bank interleaving enabled */
804 .sde_to_rst
= 0x10, /* 14 cycles, 200us (JEDEC default) */
805 .rst_to_cke
= 0x23, /* 33 cycles, 500us (JEDEC default) */
806 .ddr_type
= DDR_TYPE_DDR3
,
807 .refsel
= 0, /* Refresh cycles at 64KHz */
808 .refr
= 1, /* 2 refresh commands per refresh cycle */
811 static struct mx6_ddr3_cfg mem_ddr
= {
825 static void ccgr_init(void)
827 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
829 writel(0xFFFFFFFF, &ccm
->CCGR0
);
830 writel(0xFFFFFFFF, &ccm
->CCGR1
);
831 writel(0xFFFFFFFF, &ccm
->CCGR2
);
832 writel(0xFFFFFFFF, &ccm
->CCGR3
);
833 writel(0xFFFFFFFF, &ccm
->CCGR4
);
834 writel(0xFFFFFFFF, &ccm
->CCGR5
);
835 writel(0xFFFFFFFF, &ccm
->CCGR6
);
836 writel(0xFFFFFFFF, &ccm
->CCGR7
);
839 static void spl_dram_init(void)
841 mx6ul_dram_iocfg(mem_ddr
.width
, &mx6_ddr_ioregs
, &mx6_grp_ioregs
);
842 mx6_dram_cfg(&ddr_sysinfo
, &mx6_mmcd_calib
, &mem_ddr
);
845 void board_init_f(ulong dummy
)
849 /* setup AIPS and disable watchdog */
852 /* iomux and setup of i2c */
853 board_early_init_f();
858 /* UART clocks enabled and gd valid - init serial console */
859 preloader_console_init();
861 /* DDR initialization */
865 memset(__bss_start
, 0, __bss_end
- __bss_start
);
867 /* load/boot image from boot device */
868 board_init_r(NULL
, 0);