2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/immap_85xx.h>
31 #include <fdt_support.h>
37 #include <asm/fsl_serdes.h>
38 #include <asm/fsl_ifc.h>
39 #include <asm/fsl_pci.h>
45 DECLARE_GLOBAL_DATA_PTR
;
47 #define GPIO4_PCIE_RESET_SET 0x08000000
48 #define MUX_CPLD_CAN_UART 0x00
49 #define MUX_CPLD_TDM 0x01
50 #define MUX_CPLD_SPICS0_FLASH 0x00
51 #define MUX_CPLD_SPICS0_SLIC 0x02
55 u8 cpld_ver
; /* cpld revision */
56 u8 pcba_ver
; /* pcb revision number */
59 u8 bank_sel
; /* NOR Flash bank */
65 u8 spi_cs0_sel
; /* SPI CS0 SLIC/SPI Flash */
66 u8 por0
; /* POR Options */
67 u8 por1
; /* POR Options */
68 u8 por2
; /* POR Options */
69 u8 por3
; /* POR Options */
74 struct cpld_data
*cpld_data
= (void *)(CONFIG_SYS_CPLD_BASE
);
76 printf("CPLD: V%x.%x PCBA: V%x.0\n",
77 in_8(&cpld_data
->cpld_ver
) & 0xF0,
78 in_8(&cpld_data
->cpld_ver
) & 0x0F,
79 in_8(&cpld_data
->pcba_ver
) & 0x0F);
82 printf("twindie_ddr =%x\n",
83 in_8(&cpld_data
->twindie_ddr3
));
84 printf("bank_sel =%x\n",
85 in_8(&cpld_data
->bank_sel
));
86 printf("usb2_sel =%x\n",
87 in_8(&cpld_data
->usb2_sel
));
88 printf("porsw_sel =%x\n",
89 in_8(&cpld_data
->porsw_sel
));
90 printf("tdm_can_sel =%x\n",
91 in_8(&cpld_data
->tdm_can_sel
));
92 printf("tdm_can_sel =%x\n",
93 in_8(&cpld_data
->tdm_can_sel
));
94 printf("spi_cs0_sel =%x\n",
95 in_8(&cpld_data
->spi_cs0_sel
));
97 in_8(&cpld_data
->bcsr0
));
99 in_8(&cpld_data
->bcsr1
));
100 printf("bcsr2 =%x\n",
101 in_8(&cpld_data
->bcsr2
));
102 printf("bcsr3 =%x\n",
103 in_8(&cpld_data
->bcsr3
));
108 int board_early_init_f(void)
110 ccsr_gpio_t
*pgpio
= (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
);
111 #ifndef CONFIG_SDCARD
112 struct fsl_ifc
*ifc
= (void *)CONFIG_SYS_IFC_ADDR
;
114 /* Clock configuration to access CPLD using IFC(GPCM) */
115 setbits_be32(&ifc
->ifc_gcr
, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT
);
118 * Reset PCIe slots via GPIO4
120 setbits_be32(&pgpio
->gpdir
, GPIO4_PCIE_RESET_SET
);
121 setbits_be32(&pgpio
->gpdat
, GPIO4_PCIE_RESET_SET
);
126 int board_early_init_r(void)
128 #ifndef CONFIG_SDCARD
129 const unsigned int flashbase
= CONFIG_SYS_FLASH_BASE
;
130 const u8 flash_esel
= find_tlb_idx((void *)flashbase
, 1);
133 * Remap Boot flash region to caching-inhibited
134 * so that flash can be erased properly.
137 /* Flush d-cache and invalidate i-cache of any FLASH data */
141 /* invalidate existing TLB entry for flash */
142 disable_tlb(flash_esel
);
144 set_tlb(1, flashbase
, CONFIG_SYS_FLASH_BASE_PHYS
,
145 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
146 0, flash_esel
, BOOKE_PAGESZ_16M
, 1);
148 set_tlb(1, flashbase
+ 0x1000000,
149 CONFIG_SYS_FLASH_BASE_PHYS
+ 0x1000000,
150 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
151 0, flash_esel
+1, BOOKE_PAGESZ_16M
, 1);
157 void pci_init_board(void)
159 fsl_pcie_init_board(0);
161 #endif /* ifdef CONFIG_PCI */
165 struct cpu_type
*cpu
;
168 printf("Board: %sRDB ", cpu
->name
);
169 #ifdef CONFIG_PHYS_64BIT
170 puts("(36-bit addrmap)");
177 #ifdef CONFIG_TSEC_ENET
178 int board_eth_init(bd_t
*bis
)
180 struct fsl_pq_mdio_info mdio_info
;
181 struct tsec_info_struct tsec_info
[4];
182 struct cpu_type
*cpu
;
188 SET_STD_TSEC_INFO(tsec_info
[num
], 1);
192 SET_STD_TSEC_INFO(tsec_info
[num
], 2);
196 /* P1014 and it's derivatives do not support eTSEC3 */
197 if (cpu
->soc_ver
!= SVR_P1014
&& cpu
->soc_ver
!= SVR_P1014_E
) {
198 SET_STD_TSEC_INFO(tsec_info
[num
], 3);
203 printf("No TSECs initialized\n");
207 mdio_info
.regs
= (struct tsec_mii_mng
*)CONFIG_SYS_MDIO_BASE_ADDR
;
208 mdio_info
.name
= DEFAULT_MII_NAME
;
210 fsl_pq_mdio_init(bis
, &mdio_info
);
212 tsec_eth_init(bis
, tsec_info
, num
);
214 return pci_eth_init(bis
);
218 #if defined(CONFIG_OF_BOARD_SETUP)
219 void fdt_del_flexcan(void *blob
)
223 while ((nodeoff
= fdt_node_offset_by_compatible(blob
, 0,
224 "fsl,flexcan-v1.0")) >= 0) {
225 fdt_del_node(blob
, nodeoff
);
229 void fdt_del_spi_flash(void *blob
)
233 while ((nodeoff
= fdt_node_offset_by_compatible(blob
, 0,
234 "spansion,s25sl12801")) >= 0) {
235 fdt_del_node(blob
, nodeoff
);
239 void fdt_del_spi_slic(void *blob
)
243 while ((nodeoff
= fdt_node_offset_by_compatible(blob
, 0,
244 "zarlink,le88266")) >= 0) {
245 fdt_del_node(blob
, nodeoff
);
249 void fdt_del_tdm(void *blob
)
253 while ((nodeoff
= fdt_node_offset_by_compatible(blob
, 0,
254 "fsl,starlite-tdm")) >= 0) {
255 fdt_del_node(blob
, nodeoff
);
259 void ft_board_setup(void *blob
, bd_t
*bd
)
263 struct cpu_type
*cpu
;
267 ft_cpu_setup(blob
, bd
);
269 base
= getenv_bootm_low();
270 size
= getenv_bootm_size();
272 #if defined(CONFIG_PCI)
276 fdt_fixup_memory(blob
, (u64
)base
, (u64
)size
);
278 #if defined(CONFIG_HAS_FSL_DR_USB)
279 fdt_fixup_dr_usb(blob
, bd
);
282 /* P1014 and it's derivatives don't support CAN and eTSEC3 */
283 if (cpu
->soc_ver
== SVR_P1014
|| cpu
->soc_ver
== SVR_P1014_E
) {
284 fdt_del_flexcan(blob
);
285 fdt_del_node_and_alias(blob
, "ethernet2");
287 #ifndef CONFIG_SDCARD
288 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
291 fdt_del_spi_slic(blob
);
293 #ifndef CONFIG_SPIFLASH
294 else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
296 fdt_del_flexcan(blob
);
297 fdt_del_spi_flash(blob
);
304 #ifndef CONFIG_SDCARD
305 int misc_init_r(void)
307 struct cpld_data
*cpld_data
= (void *)(CONFIG_SYS_CPLD_BASE
);
308 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
310 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
311 clrbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_CAN1_TDM
|
312 MPC85xx_PMUXCR_CAN1_UART
|
313 MPC85xx_PMUXCR_CAN2_TDM
|
314 MPC85xx_PMUXCR_CAN2_UART
);
315 out_8(&cpld_data
->tdm_can_sel
, MUX_CPLD_CAN_UART
);
317 #ifndef CONFIG_SPIFLASH
318 if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
320 clrbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_CAN2_UART
|
321 MPC85xx_PMUXCR_CAN1_UART
);
322 setbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_CAN2_TDM
|
323 MPC85xx_PMUXCR_CAN1_TDM
);
324 clrbits_be32(&gur
->pmuxcr2
, MPC85xx_PMUXCR2_UART_GPIO
);
325 setbits_be32(&gur
->pmuxcr2
, MPC85xx_PMUXCR2_UART_TDM
);
326 out_8(&cpld_data
->tdm_can_sel
, MUX_CPLD_TDM
);
327 out_8(&cpld_data
->spi_cs0_sel
, MUX_CPLD_SPICS0_SLIC
);