board/freescale/p1010rdb/p1010rdb.c

   1 /*
   2  * Copyright 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/processor.h>
   9 #include <asm/mmu.h>
  10 #include <asm/cache.h>
  11 #include <asm/immap_85xx.h>
  12 #include <asm/io.h>
  13 #include <miiphy.h>
  14 #include <libfdt.h>
  15 #include <fdt_support.h>
  16 #include <fsl_mdio.h>
  17 #include <tsec.h>
  18 #include <mmc.h>
  19 #include <netdev.h>
  20 #include <pci.h>
  21 #include <asm/fsl_serdes.h>
  22 #include <fsl_ifc.h>
  23 #include <asm/fsl_pci.h>
  24 #include <hwconfig.h>
  25 #include <i2c.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define GPIO4_PCIE_RESET_SET            0x08000000
  30 #define MUX_CPLD_CAN_UART               0x00
  31 #define MUX_CPLD_TDM                    0x01
  32 #define MUX_CPLD_SPICS0_FLASH           0x00
  33 #define MUX_CPLD_SPICS0_SLIC            0x02
  34 #define PMUXCR1_IFC_MASK       0x00ffff00
  35 #define PMUXCR1_SDHC_MASK      0x00fff000
  36 #define PMUXCR1_SDHC_ENABLE    0x00555000
  37
  38 enum {
  39         MUX_TYPE_IFC,
  40         MUX_TYPE_SDHC,
  41         MUX_TYPE_SPIFLASH,
  42         MUX_TYPE_TDM,
  43         MUX_TYPE_CAN,
  44         MUX_TYPE_CS0_NOR,
  45         MUX_TYPE_CS0_NAND,
  46 };
  47
  48 enum {
  49         I2C_READ_BANK,
  50         I2C_READ_PCB_VER,
  51 };
  52
  53 static uint sd_ifc_mux;
  54
  55 struct cpld_data {
  56         u8 cpld_ver; /* cpld revision */
  57 #if defined(CONFIG_P1010RDB_PA)
  58         u8 pcba_ver; /* pcb revision number */
  59         u8 twindie_ddr3;
  60         u8 res1[6];
  61         u8 bank_sel; /* NOR Flash bank */
  62         u8 res2[5];
  63         u8 usb2_sel;
  64         u8 res3[1];
  65         u8 porsw_sel;
  66         u8 tdm_can_sel;
  67         u8 spi_cs0_sel; /* SPI CS0 SLIC/SPI Flash */
  68         u8 por0; /* POR Options */
  69         u8 por1; /* POR Options */
  70         u8 por2; /* POR Options */
  71         u8 por3; /* POR Options */
  72 #elif defined(CONFIG_P1010RDB_PB)
  73         u8 rom_loc;
  74 #endif
  75 };
  76
  77 int board_early_init_f(void)
  78 {
  79         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  80         struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
  81
  82         /* Clock configuration to access CPLD using IFC(GPCM) */
  83         setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  84         /*
  85         * Reset PCIe slots via GPIO4
  86         */
  87         setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET);
  88         setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET);
  89
  90         return 0;
  91 }
  92
  93 int board_early_init_r(void)
  94 {
  95         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  96         int flash_esel = find_tlb_idx((void *)flashbase, 1);
  97
  98         /*
  99          * Remap Boot flash region to caching-inhibited
 100          * so that flash can be erased properly.
 101          */
 102
 103         /* Flush d-cache and invalidate i-cache of any FLASH data */
 104         flush_dcache();
 105         invalidate_icache();
 106
 107         if (flash_esel == -1) {
 108                 /* very unlikely unless something is messed up */
 109                 puts("Error: Could not find TLB for FLASH BASE\n");
 110                 flash_esel = 2; /* give our best effort to continue */
 111         } else {
 112                 /* invalidate existing TLB entry for flash */
 113                 disable_tlb(flash_esel);
 114         }
 115
 116         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 117                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 118                         0, flash_esel, BOOKE_PAGESZ_16M, 1);
 119
 120         set_tlb(1, flashbase + 0x1000000,
 121                         CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
 122                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 123                         0, flash_esel+1, BOOKE_PAGESZ_16M, 1);
 124         return 0;
 125 }
 126
 127 #ifdef CONFIG_PCI
 128 void pci_init_board(void)
 129 {
 130         fsl_pcie_init_board(0);
 131 }
 132 #endif /* ifdef CONFIG_PCI */
 133
 134 int config_board_mux(int ctrl_type)
 135 {
 136         ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 137         u8 tmp;
 138
 139 #if defined(CONFIG_P1010RDB_PA)
 140         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 141
 142         switch (ctrl_type) {
 143         case MUX_TYPE_IFC:
 144                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 145                 tmp = 0xf0;
 146                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 147                 tmp = 0x01;
 148                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 149                 sd_ifc_mux = MUX_TYPE_IFC;
 150                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 151                 break;
 152         case MUX_TYPE_SDHC:
 153                 i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 154                 tmp = 0xf0;
 155                 i2c_write(I2C_PCA9557_ADDR1, 3, 1, &tmp, 1);
 156                 tmp = 0x05;
 157                 i2c_write(I2C_PCA9557_ADDR1, 1, 1, &tmp, 1);
 158                 sd_ifc_mux = MUX_TYPE_SDHC;
 159                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 160                                 PMUXCR1_SDHC_ENABLE);
 161                 break;
 162         case MUX_TYPE_SPIFLASH:
 163                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH);
 164                 break;
 165         case MUX_TYPE_TDM:
 166                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM);
 167                 out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC);
 168                 break;
 169         case MUX_TYPE_CAN:
 170                 out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART);
 171                 break;
 172         default:
 173                 break;
 174         }
 175 #elif defined(CONFIG_P1010RDB_PB)
 176         uint orig_bus = i2c_get_bus_num();
 177         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 178
 179         switch (ctrl_type) {
 180         case MUX_TYPE_IFC:
 181                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 182                 clrbits_8(&tmp, 0x04);
 183                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 184                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 185                 clrbits_8(&tmp, 0x04);
 186                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 187                 sd_ifc_mux = MUX_TYPE_IFC;
 188                 clrbits_be32(&gur->pmuxcr, PMUXCR1_IFC_MASK);
 189                 break;
 190         case MUX_TYPE_SDHC:
 191                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 192                 setbits_8(&tmp, 0x04);
 193                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 194                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 195                 clrbits_8(&tmp, 0x04);
 196                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 197                 sd_ifc_mux = MUX_TYPE_SDHC;
 198                 clrsetbits_be32(&gur->pmuxcr, PMUXCR1_SDHC_MASK,
 199                                 PMUXCR1_SDHC_ENABLE);
 200                 break;
 201         case MUX_TYPE_SPIFLASH:
 202                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 203                 clrbits_8(&tmp, 0x80);
 204                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 205                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 206                 clrbits_8(&tmp, 0x80);
 207                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 208                 break;
 209         case MUX_TYPE_TDM:
 210                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 211                 setbits_8(&tmp, 0x82);
 212                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 213                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 214                 clrbits_8(&tmp, 0x82);
 215                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 216                 break;
 217         case MUX_TYPE_CAN:
 218                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 219                 clrbits_8(&tmp, 0x02);
 220                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 221                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 222                 clrbits_8(&tmp, 0x02);
 223                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 224                 break;
 225         case MUX_TYPE_CS0_NOR:
 226                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 227                 clrbits_8(&tmp, 0x08);
 228                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 229                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 230                 clrbits_8(&tmp, 0x08);
 231                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 232                 break;
 233         case MUX_TYPE_CS0_NAND:
 234                 i2c_read(I2C_PCA9557_ADDR2, 0, 1, &tmp, 1);
 235                 setbits_8(&tmp, 0x08);
 236                 i2c_write(I2C_PCA9557_ADDR2, 1, 1, &tmp, 1);
 237                 i2c_read(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 238                 clrbits_8(&tmp, 0x08);
 239                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &tmp, 1);
 240                 break;
 241         default:
 242                 break;
 243         }
 244         i2c_set_bus_num(orig_bus);
 245 #endif
 246         return 0;
 247 }
 248
 249 #ifdef CONFIG_P1010RDB_PB
 250 int i2c_pca9557_read(int type)
 251 {
 252         u8 val;
 253
 254         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 255         i2c_read(I2C_PCA9557_ADDR2, 0, 1, &val, 1);
 256
 257         switch (type) {
 258         case I2C_READ_BANK:
 259                 val = (val & 0x10) >> 4;
 260                 break;
 261         case I2C_READ_PCB_VER:
 262                 val = ((val & 0x60) >> 5) + 1;
 263                 break;
 264         default:
 265                 break;
 266         }
 267
 268         return val;
 269 }
 270 #endif
 271
 272 int checkboard(void)
 273 {
 274         struct cpu_type *cpu;
 275         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 276         u8 val;
 277
 278         cpu = gd->arch.cpu;
 279 #if defined(CONFIG_P1010RDB_PA)
 280         printf("Board: %sRDB-PA, ", cpu->name);
 281 #elif defined(CONFIG_P1010RDB_PB)
 282         printf("Board: %sRDB-PB, ", cpu->name);
 283         i2c_set_bus_num(I2C_PCA9557_BUS_NUM);
 284         i2c_init(CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE);
 285         val = 0x0;  /* no polarity inversion */
 286         i2c_write(I2C_PCA9557_ADDR2, 2, 1, &val, 1);
 287 #endif
 288
 289 #ifdef CONFIG_SDCARD
 290         /* switch to IFC to read info from CPLD */
 291         config_board_mux(MUX_TYPE_IFC);
 292 #endif
 293
 294 #if defined(CONFIG_P1010RDB_PA)
 295         val = (in_8(&cpld_data->pcba_ver) & 0xf);
 296         printf("PCB: v%x.0\n", val);
 297 #elif defined(CONFIG_P1010RDB_PB)
 298         val = in_8(&cpld_data->cpld_ver);
 299         printf("CPLD: v%x.%x, ", val >> 4, val & 0xf);
 300         printf("PCB: v%x.0, ", i2c_pca9557_read(I2C_READ_PCB_VER));
 301         val = in_8(&cpld_data->rom_loc) & 0xf;
 302         puts("Boot from: ");
 303         switch (val) {
 304         case 0xf:
 305                 config_board_mux(MUX_TYPE_CS0_NOR);
 306                 printf("NOR vBank%d\n", i2c_pca9557_read(I2C_READ_BANK));
 307                 break;
 308         case 0xe:
 309                 puts("SDHC\n");
 310                 val = 0x60; /* set pca9557 pin input/output */
 311                 i2c_write(I2C_PCA9557_ADDR2, 3, 1, &val, 1);
 312                 break;
 313         case 0x5:
 314                 config_board_mux(MUX_TYPE_IFC);
 315                 config_board_mux(MUX_TYPE_CS0_NAND);
 316                 puts("NAND\n");
 317                 break;
 318         case 0x6:
 319                 config_board_mux(MUX_TYPE_IFC);
 320                 puts("SPI\n");
 321                 break;
 322         default:
 323                 puts("unknown\n");
 324                 break;
 325         }
 326 #endif
 327         return 0;
 328 }
 329
 330 #ifdef CONFIG_TSEC_ENET
 331 int board_eth_init(bd_t *bis)
 332 {
 333         struct fsl_pq_mdio_info mdio_info;
 334         struct tsec_info_struct tsec_info[4];
 335         struct cpu_type *cpu;
 336         int num = 0;
 337
 338         cpu = gd->arch.cpu;
 339
 340 #ifdef CONFIG_TSEC1
 341         SET_STD_TSEC_INFO(tsec_info[num], 1);
 342         num++;
 343 #endif
 344 #ifdef CONFIG_TSEC2
 345         SET_STD_TSEC_INFO(tsec_info[num], 2);
 346         num++;
 347 #endif
 348 #ifdef CONFIG_TSEC3
 349         /* P1014 and it's derivatives do not support eTSEC3 */
 350         if (cpu->soc_ver != SVR_P1014) {
 351                 SET_STD_TSEC_INFO(tsec_info[num], 3);
 352                 num++;
 353         }
 354 #endif
 355         if (!num) {
 356                 printf("No TSECs initialized\n");
 357                 return 0;
 358         }
 359
 360         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 361         mdio_info.name = DEFAULT_MII_NAME;
 362
 363         fsl_pq_mdio_init(bis, &mdio_info);
 364
 365         tsec_eth_init(bis, tsec_info, num);
 366
 367         return pci_eth_init(bis);
 368 }
 369 #endif
 370
 371 #if defined(CONFIG_OF_BOARD_SETUP)
 372 void fdt_del_flexcan(void *blob)
 373 {
 374         int nodeoff = 0;
 375
 376         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 377                                 "fsl,p1010-flexcan")) >= 0) {
 378                 fdt_del_node(blob, nodeoff);
 379         }
 380 }
 381
 382 void fdt_del_spi_flash(void *blob)
 383 {
 384         int nodeoff = 0;
 385
 386         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 387                                 "spansion,s25sl12801")) >= 0) {
 388                 fdt_del_node(blob, nodeoff);
 389         }
 390 }
 391
 392 void fdt_del_spi_slic(void *blob)
 393 {
 394         int nodeoff = 0;
 395
 396         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 397                                 "zarlink,le88266")) >= 0) {
 398                 fdt_del_node(blob, nodeoff);
 399         }
 400 }
 401
 402 void fdt_del_tdm(void *blob)
 403 {
 404         int nodeoff = 0;
 405
 406         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 407                                 "fsl,starlite-tdm")) >= 0) {
 408                 fdt_del_node(blob, nodeoff);
 409         }
 410 }
 411
 412 void fdt_del_sdhc(void *blob)
 413 {
 414         int nodeoff = 0;
 415
 416         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 417                         "fsl,esdhc")) >= 0) {
 418                 fdt_del_node(blob, nodeoff);
 419         }
 420 }
 421
 422 void fdt_del_ifc(void *blob)
 423 {
 424         int nodeoff = 0;
 425
 426         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 427                                 "fsl,ifc")) >= 0) {
 428                 fdt_del_node(blob, nodeoff);
 429         }
 430 }
 431
 432 void fdt_disable_uart1(void *blob)
 433 {
 434         int nodeoff;
 435
 436         nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,ns16550",
 437                                         CONFIG_SYS_NS16550_COM2);
 438
 439         if (nodeoff > 0) {
 440                 fdt_status_disabled(blob, nodeoff);
 441         } else {
 442                 printf("WARNING unable to set status for fsl,ns16550 "
 443                         "uart1: %s\n", fdt_strerror(nodeoff));
 444         }
 445 }
 446
 447 int ft_board_setup(void *blob, bd_t *bd)
 448 {
 449         phys_addr_t base;
 450         phys_size_t size;
 451         struct cpu_type *cpu;
 452
 453         cpu = gd->arch.cpu;
 454
 455         ft_cpu_setup(blob, bd);
 456
 457         base = getenv_bootm_low();
 458         size = getenv_bootm_size();
 459
 460 #if defined(CONFIG_PCI)
 461         FT_FSL_PCI_SETUP;
 462 #endif
 463
 464         fdt_fixup_memory(blob, (u64)base, (u64)size);
 465
 466 #if defined(CONFIG_HAS_FSL_DR_USB)
 467         fdt_fixup_dr_usb(blob, bd);
 468 #endif
 469
 470        /* P1014 and it's derivatives don't support CAN and eTSEC3 */
 471         if (cpu->soc_ver == SVR_P1014) {
 472                 fdt_del_flexcan(blob);
 473                 fdt_del_node_and_alias(blob, "ethernet2");
 474         }
 475
 476         /* Delete IFC node as IFC pins are multiplexing with SDHC */
 477         if (sd_ifc_mux != MUX_TYPE_IFC)
 478                 fdt_del_ifc(blob);
 479         else
 480                 fdt_del_sdhc(blob);
 481
 482         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 483                 fdt_del_tdm(blob);
 484                 fdt_del_spi_slic(blob);
 485         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 486                 fdt_del_flexcan(blob);
 487                 fdt_del_spi_flash(blob);
 488                 fdt_disable_uart1(blob);
 489         } else {
 490                 /*
 491                  * If we don't set fsl_p1010mux:tdm_can to "can" or "tdm"
 492                  * explicitly, defaultly spi_cs_sel to spi-flash instead of
 493                  * to tdm/slic.
 494                  */
 495                 fdt_del_tdm(blob);
 496                 fdt_del_flexcan(blob);
 497                 fdt_disable_uart1(blob);
 498         }
 499
 500         return 0;
 501 }
 502 #endif
 503
 504 #ifdef CONFIG_SDCARD
 505 int board_mmc_init(bd_t *bis)
 506 {
 507         config_board_mux(MUX_TYPE_SDHC);
 508                 return -1;
 509 }
 510 #else
 511 void board_reset(void)
 512 {
 513         /* mux to IFC to enable CPLD for reset */
 514         if (sd_ifc_mux != MUX_TYPE_IFC)
 515                 config_board_mux(MUX_TYPE_IFC);
 516 }
 517 #endif
 518
 519
 520 int misc_init_r(void)
 521 {
 522         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 523
 524         if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) {
 525                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM |
 526                                 MPC85xx_PMUXCR_CAN1_UART |
 527                                 MPC85xx_PMUXCR_CAN2_TDM |
 528                                 MPC85xx_PMUXCR_CAN2_UART);
 529                 config_board_mux(MUX_TYPE_CAN);
 530         } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) {
 531                 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART |
 532                                 MPC85xx_PMUXCR_CAN1_UART);
 533                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM |
 534                                 MPC85xx_PMUXCR_CAN1_TDM);
 535                 clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO);
 536                 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM);
 537                 config_board_mux(MUX_TYPE_TDM);
 538         } else {
 539                 /* defaultly spi_cs_sel to flash */
 540                 config_board_mux(MUX_TYPE_SPIFLASH);
 541         }
 542
 543         if (hwconfig("esdhc"))
 544                 config_board_mux(MUX_TYPE_SDHC);
 545         else if (hwconfig("ifc"))
 546                 config_board_mux(MUX_TYPE_IFC);
 547
 548 #ifdef CONFIG_P1010RDB_PB
 549         setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
 550 #endif
 551         return 0;
 552 }
 553
 554 static int pin_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 555                                 char * const argv[])
 556 {
 557         if (argc < 2)
 558                 return CMD_RET_USAGE;
 559         if (strcmp(argv[1], "ifc") == 0)
 560                 config_board_mux(MUX_TYPE_IFC);
 561         else if (strcmp(argv[1], "sdhc") == 0)
 562                 config_board_mux(MUX_TYPE_SDHC);
 563         else
 564                 return CMD_RET_USAGE;
 565         return 0;
 566 }
 567
 568 U_BOOT_CMD(
 569         mux, 2, 0, pin_mux_cmd,
 570         "configure multiplexing pin for IFC/SDHC bus in runtime",
 571         "bus_type (e.g. mux sdhc)"
 572 );