2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 struct fsl_e_tlb_entry tlb_table
[] = {
11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
, CONFIG_SYS_INIT_RAM_ADDR
,
13 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
14 0, 0, BOOKE_PAGESZ_4K
, 0),
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 4 * 1024,
16 CONFIG_SYS_INIT_RAM_ADDR
+ 4 * 1024,
17 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
18 0, 0, BOOKE_PAGESZ_4K
, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 8 * 1024,
20 CONFIG_SYS_INIT_RAM_ADDR
+ 8 * 1024,
21 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
22 0, 0, BOOKE_PAGESZ_4K
, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 12 * 1024,
24 CONFIG_SYS_INIT_RAM_ADDR
+ 12 * 1024,
25 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
26 0, 0, BOOKE_PAGESZ_4K
, 0),
29 /* *I*** - Covers boot page */
30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
31 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
,
32 0, 0, BOOKE_PAGESZ_4K
, 1),
35 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR
, CONFIG_SYS_CCSRBAR_PHYS
,
36 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
37 0, 1, BOOKE_PAGESZ_4M
, 1),
39 /* W**G* - Flash, localbus */
40 /* This will be changed to *I*G* after relocation to RAM. */
41 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FLASH_BASE_PHYS
,
42 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_W
|MAS2_G
,
43 0, 2, BOOKE_PAGESZ_256M
, 1),
46 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT
, CONFIG_SYS_PCIE3_MEM_PHYS
,
47 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
48 0, 3, BOOKE_PAGESZ_1G
, 1),
51 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT
+ 0x40000000,
52 CONFIG_SYS_PCIE3_MEM_PHYS
+ 0x40000000,
53 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
54 0, 4, BOOKE_PAGESZ_256M
, 1),
56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT
+ 0x50000000,
57 CONFIG_SYS_PCIE3_MEM_PHYS
+ 0x50000000,
58 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
59 0, 5, BOOKE_PAGESZ_256M
, 1),
62 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT
, CONFIG_SYS_PCIE3_IO_PHYS
,
63 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
64 0, 6, BOOKE_PAGESZ_256K
, 1),
67 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
, CONFIG_SYS_BMAN_MEM_PHYS
,
69 0, 7, BOOKE_PAGESZ_1M
, 1),
70 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
+ 0x00100000,
71 CONFIG_SYS_BMAN_MEM_PHYS
+ 0x00100000,
72 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
73 0, 8, BOOKE_PAGESZ_1M
, 1),
74 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
, CONFIG_SYS_QMAN_MEM_PHYS
,
75 MAS3_SW
|MAS3_SR
, MAS2_M
,
76 0, 9, BOOKE_PAGESZ_1M
, 1),
77 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
+ 0x00100000,
78 CONFIG_SYS_QMAN_MEM_PHYS
+ 0x00100000,
79 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
80 0, 10, BOOKE_PAGESZ_1M
, 1),
82 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE
, CONFIG_SYS_NAND_BASE_PHYS
,
83 MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
84 0, 11, BOOKE_PAGESZ_16K
, 1),
86 #ifdef CONFIG_SYS_RAMBOOT
87 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE
,
88 CONFIG_SYS_DDR_SDRAM_BASE
,
89 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
90 0, 12, BOOKE_PAGESZ_256M
, 1),
92 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE
+ 0x10000000,
93 CONFIG_SYS_DDR_SDRAM_BASE
+ 0x10000000,
94 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
95 0, 13, BOOKE_PAGESZ_256M
, 1),
99 int num_tlb_entries
= ARRAY_SIZE(tlb_table
);