2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 struct fsl_e_tlb_entry tlb_table
[] = {
27 /* TLB 0 - for temp stack in cache */
28 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
, CONFIG_SYS_INIT_RAM_ADDR
,
29 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
30 0, 0, BOOKE_PAGESZ_4K
, 0),
31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 4 * 1024,
32 CONFIG_SYS_INIT_RAM_ADDR
+ 4 * 1024,
33 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
34 0, 0, BOOKE_PAGESZ_4K
, 0),
35 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 8 * 1024,
36 CONFIG_SYS_INIT_RAM_ADDR
+ 8 * 1024,
37 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
38 0, 0, BOOKE_PAGESZ_4K
, 0),
39 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 12 * 1024,
40 CONFIG_SYS_INIT_RAM_ADDR
+ 12 * 1024,
41 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
42 0, 0, BOOKE_PAGESZ_4K
, 0),
45 /* *I*** - Covers boot page */
46 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
47 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
,
48 0, 0, BOOKE_PAGESZ_4K
, 1),
51 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR
, CONFIG_SYS_CCSRBAR_PHYS
,
52 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
53 0, 1, BOOKE_PAGESZ_4M
, 1),
55 #ifndef CONFIG_NAND_SPL
56 /* *W*G* - BCSR and NOR flash on local bus*/
57 /* This will be changed to *I*G* after relocation to RAM. */
58 SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE
, CONFIG_SYS_BCSR_BASE_PHYS
,
59 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_W
|MAS2_G
,
60 0, 2, BOOKE_PAGESZ_256M
, 1),
63 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT
, CONFIG_SYS_PCIE3_MEM_PHYS
,
64 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
65 0, 3, BOOKE_PAGESZ_1G
, 1),
68 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT
+ 0x40000000,
69 CONFIG_SYS_PCIE3_MEM_PHYS
+ 0x40000000,
70 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
71 0, 4, BOOKE_PAGESZ_256M
, 1),
73 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT
+ 0x50000000,
74 CONFIG_SYS_PCIE3_MEM_PHYS
+ 0x50000000,
75 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
76 0, 5, BOOKE_PAGESZ_256M
, 1),
79 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT
, CONFIG_SYS_PCIE3_IO_PHYS
,
80 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
81 0, 6, BOOKE_PAGESZ_256K
, 1),
84 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
, CONFIG_SYS_BMAN_MEM_PHYS
,
85 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
86 0, 7, BOOKE_PAGESZ_1M
, 1),
87 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
+ 0x00100000,
88 CONFIG_SYS_BMAN_MEM_PHYS
+ 0x00100000,
89 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
90 0, 8, BOOKE_PAGESZ_1M
, 1),
91 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
, CONFIG_SYS_QMAN_MEM_PHYS
,
92 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_M
,
93 0, 9, BOOKE_PAGESZ_1M
, 1),
94 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
+ 0x00100000,
95 CONFIG_SYS_QMAN_MEM_PHYS
+ 0x00100000,
96 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
97 0, 10, BOOKE_PAGESZ_1M
, 1),
101 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE
, CONFIG_SYS_NAND_BASE_PHYS
,
102 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
103 0, 11, BOOKE_PAGESZ_1M
, 1),
105 #ifdef CONFIG_SYS_RAMBOOT
106 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE
,
107 CONFIG_SYS_DDR_SDRAM_BASE
,
108 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
109 0, 12, BOOKE_PAGESZ_1G
, 1),
111 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE
+ 0x40000000,
112 CONFIG_SYS_DDR_SDRAM_BASE
+ 0x40000000,
113 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
114 0, 13, BOOKE_PAGESZ_1G
, 1),
118 int num_tlb_entries
= ARRAY_SIZE(tlb_table
);