board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
   4  * Copyright 2020 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <env.h>
  10 #include <hang.h>
  11 #include <hwconfig.h>
  12 #include <init.h>
  13 #include <net.h>
  14 #include <pci.h>
  15 #include <i2c.h>
  16 #include <asm/processor.h>
  17 #include <asm/mmu.h>
  18 #include <asm/cache.h>
  19 #include <asm/immap_85xx.h>
  20 #include <asm/fsl_pci.h>
  21 #include <fsl_ddr_sdram.h>
  22 #include <asm/io.h>
  23 #include <asm/fsl_law.h>
  24 #include <asm/fsl_lbc.h>
  25 #include <asm/mp.h>
  26 #include <miiphy.h>
  27 #include <linux/libfdt.h>
  28 #include <fdt_support.h>
  29 #include <fsl_mdio.h>
  30 #include <tsec.h>
  31 #include <vsc7385.h>
  32 #include <ioports.h>
  33 #include <asm/fsl_serdes.h>
  34 #include <netdev.h>
  35
  36 #ifdef CONFIG_QE
  37
  38 #define GPIO_GETH_SW_PORT       1
  39 #define GPIO_GETH_SW_PIN        29
  40 #define GPIO_GETH_SW_DATA       (1 << (31 - GPIO_GETH_SW_PIN))
  41
  42 #define GPIO_SLIC_PORT          1
  43 #define GPIO_SLIC_PIN           30
  44 #define GPIO_SLIC_DATA          (1 << (31 - GPIO_SLIC_PIN))
  45
  46 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  47 #define GPIO_DDR_RST_PORT       1
  48 #define GPIO_DDR_RST_PIN        8
  49 #define GPIO_DDR_RST_DATA       (1 << (31 - GPIO_DDR_RST_PIN))
  50
  51 #define GPIO_2BIT_MASK          (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
  52 #endif
  53
  54 #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
  55 #define PCA_IOPORT_I2C_ADDR             0x23
  56 #define PCA_IOPORT_OUTPUT_CMD           0x2
  57 #define PCA_IOPORT_CFG_CMD              0x6
  58 #define PCA_IOPORT_QE_PIN_ENABLE        0xf8
  59 #define PCA_IOPORT_QE_TDM_ENABLE        0xf6
  60 #endif
  61
  62 const qe_iop_conf_t qe_iop_conf_tab[] = {
  63         /* GPIO */
  64         {1,   1, 2, 0, 0}, /* GPIO7/PB1   - LOAD_DEFAULT_N */
  65 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
  66         {1,   8, 1, 1, 0}, /* GPIO10/PB8  - DDR_RST */
  67 #endif
  68         {0,  15, 1, 0, 0}, /* GPIO11/A15  - WDI */
  69         {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
  70         {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0},       /* RST_SLIC_N */
  71
  72 #ifdef CONFIG_TARGET_P1025RDB
  73         /* QE_MUX_MDC */
  74         {1,  19, 1, 0, 1}, /* QE_MUX_MDC               */
  75
  76         /* QE_MUX_MDIO */
  77         {1,  20, 3, 0, 1}, /* QE_MUX_MDIO              */
  78
  79         /* UCC_1_MII */
  80         {0, 23, 2, 0, 2}, /* CLK12 */
  81         {0, 24, 2, 0, 1}, /* CLK9 */
  82         {0,  7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0      */
  83         {0,  9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1      */
  84         {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2      */
  85         {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3      */
  86         {0,  6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0      */
  87         {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1      */
  88         {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2      */
  89         {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3      */
  90         {0,  5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
  91         {0, 13, 1, 0, 2}, /* ENET1_TX_ER               */
  92         {0,  4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B    */
  93         {0,  8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B    */
  94         {0, 17, 2, 0, 2}, /* ENET1_CRS    */
  95         {0, 16, 2, 0, 2}, /* ENET1_COL    */
  96
  97         /* UCC_5_RMII */
  98         {1, 11, 2, 0, 1}, /* CLK13 */
  99         {1, 7,  1, 0, 2}, /* ENET5_TXD0_SER5_TXD0      */
 100         {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1      */
 101         {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0      */
 102         {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1      */
 103         {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B    */
 104         {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B    */
 105         {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B    */
 106 #endif
 107
 108         {0,  0, 0, 0, QE_IOP_TAB_END} /* END of table */
 109 };
 110 #endif
 111
 112 struct cpld_data {
 113         u8 cpld_rev_major;
 114         u8 pcba_rev;
 115         u8 wd_cfg;
 116         u8 rst_bps_sw;
 117         u8 load_default_n;
 118         u8 rst_bps_wd;
 119         u8 bypass_enable;
 120         u8 bps_led;
 121         u8 status_led;                  /* offset: 0x8 */
 122         u8 fxo_led;                     /* offset: 0x9 */
 123         u8 fxs_led;                     /* offset: 0xa */
 124         u8 rev4[2];
 125         u8 system_rst;                  /* offset: 0xd */
 126         u8 bps_out;
 127         u8 rev5[3];
 128         u8 cpld_rev_minor;
 129 };
 130
 131 #define CPLD_WD_CFG     0x03
 132 #define CPLD_RST_BSW    0x00
 133 #define CPLD_RST_BWD    0x00
 134 #define CPLD_BYPASS_EN  0x03
 135 #define CPLD_STATUS_LED 0x01
 136 #define CPLD_FXO_LED    0x01
 137 #define CPLD_FXS_LED    0x0F
 138 #define CPLD_SYS_RST    0x00
 139
 140 void board_cpld_init(void)
 141 {
 142         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 143
 144         out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
 145         out_8(&cpld_data->status_led, CPLD_STATUS_LED);
 146         out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
 147         out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
 148         out_8(&cpld_data->system_rst, CPLD_SYS_RST);
 149 }
 150
 151 void board_gpio_init(void)
 152 {
 153 #ifdef CONFIG_QE
 154         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 155         par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
 156
 157 #if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
 158         /* reset DDR3 */
 159         setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
 160         udelay(1000);
 161         clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
 162         udelay(1000);
 163         setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
 164         /* disable CE_PB8 */
 165         clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
 166 #endif
 167         /* Enable VSC7385 switch */
 168         setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
 169
 170         /* Enable SLIC */
 171         setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
 172 #else
 173
 174         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
 175
 176         /*
 177          * GPIO10 DDR Reset, open drain
 178          * GPIO7  LOAD_DEFAULT_N          Input
 179          * GPIO11  WDI (watchdog input)
 180          * GPIO12  Ethernet Switch Reset
 181          * GPIO13  SLIC Reset
 182          */
 183
 184         setbits_be32(&pgpio->gpdir, 0x02130000);
 185 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
 186         /* init DDR3 reset signal */
 187         setbits_be32(&pgpio->gpdir, 0x00200000);
 188         setbits_be32(&pgpio->gpodr, 0x00200000);
 189         clrbits_be32(&pgpio->gpdat, 0x00200000);
 190         udelay(1000);
 191         setbits_be32(&pgpio->gpdat, 0x00200000);
 192         udelay(1000);
 193         clrbits_be32(&pgpio->gpdir, 0x00200000);
 194 #endif
 195
 196 #ifdef CONFIG_VSC7385_ENET
 197         /* reset VSC7385 Switch */
 198         setbits_be32(&pgpio->gpdir, 0x00080000);
 199         setbits_be32(&pgpio->gpdat, 0x00080000);
 200 #endif
 201
 202 #ifdef CONFIG_SLIC
 203         /* reset SLIC */
 204         setbits_be32(&pgpio->gpdir, 0x00040000);
 205         setbits_be32(&pgpio->gpdat, 0x00040000);
 206 #endif
 207 #endif
 208 }
 209
 210 int board_early_init_f(void)
 211 {
 212         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 213
 214         setbits_be32(&gur->pmuxcr,
 215                         (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
 216         clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
 217
 218         clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
 219         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
 220
 221         board_gpio_init();
 222         board_cpld_init();
 223
 224         return 0;
 225 }
 226
 227 int checkboard(void)
 228 {
 229         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 230         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 231         u8 in, out, io_config, val;
 232         int bus_num = CONFIG_SYS_SPD_BUS_NUM;
 233
 234         printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
 235                 in_8(&cpld_data->cpld_rev_major) & 0x0F,
 236                 in_8(&cpld_data->cpld_rev_minor) & 0x0F,
 237                 in_8(&cpld_data->pcba_rev) & 0x0F);
 238
 239         /* Initialize i2c early for rom_loc and flash bank information */
 240         #if defined(CONFIG_DM_I2C)
 241         struct udevice *dev;
 242         int ret;
 243
 244         ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
 245                                       1, &dev);
 246         if (ret) {
 247                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 248                        bus_num);
 249                 return -ENXIO;
 250         }
 251
 252         if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
 253             dm_i2c_read(dev, 1, &out, 1) < 0 ||
 254             dm_i2c_read(dev, 3, &io_config, 1) < 0) {
 255                 printf("Error reading i2c boot information!\n");
 256                 return 0; /* Don't want to hang() on this error */
 257         }
 258         #else /* Non DM I2C support - will be removed */
 259         i2c_set_bus_num(bus_num);
 260
 261         if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
 262             i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
 263             i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
 264                 printf("Error reading i2c boot information!\n");
 265                 return 0; /* Don't want to hang() on this error */
 266         }
 267         #endif
 268
 269         val = (in & io_config) | (out & (~io_config));
 270
 271         puts("rom_loc: ");
 272         if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
 273                 puts("sd");
 274 #ifdef __SW_BOOT_SPI
 275         } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
 276                 puts("spi");
 277 #endif
 278 #ifdef __SW_BOOT_NAND
 279         } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
 280                 puts("nand");
 281 #endif
 282 #ifdef __SW_BOOT_PCIE
 283         } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
 284                 puts("pcie");
 285 #endif
 286         } else {
 287                 if (val & 0x2)
 288                         puts("nor lower bank");
 289                 else
 290                         puts("nor upper bank");
 291         }
 292         puts("\n");
 293
 294         if (val & 0x1) {
 295                 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
 296                 puts("SD/MMC : 8-bit Mode\n");
 297                 puts("eSPI : Disabled\n");
 298         } else {
 299                 puts("SD/MMC : 4-bit Mode\n");
 300                 puts("eSPI : Enabled\n");
 301         }
 302
 303         return 0;
 304 }
 305
 306 #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
 307 void pci_init_board(void)
 308 {
 309         fsl_pcie_init_board(0);
 310 }
 311 #endif
 312
 313 int board_early_init_r(void)
 314 {
 315         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 316         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 317
 318         /*
 319          * Remap Boot flash region to caching-inhibited
 320          * so that flash can be erased properly.
 321          */
 322
 323         /* Flush d-cache and invalidate i-cache of any FLASH data */
 324         flush_dcache();
 325         invalidate_icache();
 326
 327         if (flash_esel == -1) {
 328                 /* very unlikely unless something is messed up */
 329                 puts("Error: Could not find TLB for FLASH BASE\n");
 330                 flash_esel = 2; /* give our best effort to continue */
 331         } else {
 332                 /* invalidate existing TLB entry for flash */
 333                 disable_tlb(flash_esel);
 334         }
 335
 336         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
 337                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
 338                 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
 339         return 0;
 340 }
 341
 342 int board_eth_init(bd_t *bis)
 343 {
 344         struct fsl_pq_mdio_info mdio_info;
 345         struct tsec_info_struct tsec_info[4];
 346         ccsr_gur_t *gur __attribute__((unused)) =
 347                 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 348         int num = 0;
 349 #ifdef CONFIG_VSC7385_ENET
 350         char *tmp;
 351         unsigned int vscfw_addr;
 352 #endif
 353
 354 #ifdef CONFIG_TSEC1
 355         SET_STD_TSEC_INFO(tsec_info[num], 1);
 356         num++;
 357 #endif
 358 #ifdef CONFIG_TSEC2
 359         SET_STD_TSEC_INFO(tsec_info[num], 2);
 360         if (is_serdes_configured(SGMII_TSEC2)) {
 361                 printf("eTSEC2 is in sgmii mode.\n");
 362                 tsec_info[num].flags |= TSEC_SGMII;
 363         }
 364         num++;
 365 #endif
 366 #ifdef CONFIG_TSEC3
 367         SET_STD_TSEC_INFO(tsec_info[num], 3);
 368         num++;
 369 #endif
 370
 371         if (!num) {
 372                 printf("No TSECs initialized\n");
 373                 return 0;
 374         }
 375
 376 #ifdef CONFIG_VSC7385_ENET
 377         /* If a VSC7385 microcode image is present, then upload it. */
 378         tmp = env_get("vscfw_addr");
 379         if (tmp) {
 380                 vscfw_addr = simple_strtoul(tmp, NULL, 16);
 381                 printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
 382                 if (vsc7385_upload_firmware((void *) vscfw_addr,
 383                                         CONFIG_VSC7385_IMAGE_SIZE))
 384                         puts("Failure uploading VSC7385 microcode.\n");
 385         } else
 386                 puts("No address specified for VSC7385 microcode.\n");
 387 #endif
 388
 389         mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
 390         mdio_info.name = DEFAULT_MII_NAME;
 391
 392         fsl_pq_mdio_init(bis, &mdio_info);
 393
 394         tsec_eth_init(bis, tsec_info, num);
 395
 396 #if defined(CONFIG_UEC_ETH)
 397         /*  QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
 398         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
 399         setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
 400
 401         uec_standard_init(bis);
 402 #endif
 403
 404         return pci_eth_init(bis);
 405 }
 406
 407 #if defined(CONFIG_QE) && \
 408         (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
 409 static void fdt_board_fixup_qe_pins(void *blob)
 410 {
 411         unsigned int oldbus;
 412         u8 val8;
 413         int node;
 414         fsl_lbc_t *lbc = LBC_BASE_ADDR;
 415
 416         if (hwconfig("qe")) {
 417                 /* For QE and eLBC pins multiplexing,
 418                  * there is a PCA9555 device on P1025RDB.
 419                  * It control the multiplex pins' functions,
 420                  * and setting the PCA9555 can switch the
 421                  * function between QE and eLBC.
 422                  */
 423                 oldbus = i2c_get_bus_num();
 424                 i2c_set_bus_num(0);
 425                 if (hwconfig("tdm"))
 426                         val8 = PCA_IOPORT_QE_TDM_ENABLE;
 427                 else
 428                         val8 = PCA_IOPORT_QE_PIN_ENABLE;
 429                 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
 430                                 1, &val8, 1);
 431                 i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
 432                                 1, &val8, 1);
 433                 i2c_set_bus_num(oldbus);
 434                 /* if run QE TDM, Set ABSWP to implement
 435                  * conversion of addresses in the eLBC.
 436                  */
 437                 if (hwconfig("tdm")) {
 438                         set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
 439                         set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
 440                         setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
 441                 }
 442         } else {
 443                 node = fdt_path_offset(blob, "/qe");
 444                 if (node >= 0)
 445                         fdt_del_node(blob, node);
 446         }
 447
 448         return;
 449 }
 450 #endif
 451
 452 #ifdef CONFIG_OF_BOARD_SETUP
 453 int ft_board_setup(void *blob, bd_t *bd)
 454 {
 455         phys_addr_t base;
 456         phys_size_t size;
 457 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
 458         const char *soc_usb_compat = "fsl-usb2-dr";
 459         int usb_err, usb1_off, usb2_off;
 460 #endif
 461 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 462         int err;
 463 #endif
 464
 465         ft_cpu_setup(blob, bd);
 466
 467         base = env_get_bootm_low();
 468         size = env_get_bootm_size();
 469
 470         fdt_fixup_memory(blob, (u64)base, (u64)size);
 471
 472 #if !defined(CONFIG_DM_PCI)
 473         FT_FSL_PCI_SETUP;
 474 #endif
 475
 476 #ifdef CONFIG_QE
 477         do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
 478                         sizeof("okay"), 0);
 479 #if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
 480         fdt_board_fixup_qe_pins(blob);
 481 #endif
 482 #endif
 483
 484 #if defined(CONFIG_HAS_FSL_DR_USB)
 485         fsl_fdt_fixup_dr_usb(blob, bd);
 486 #endif
 487
 488 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
 489         /* Delete eLBC node as it is muxed with USB2 controller */
 490         if (hwconfig("usb2")) {
 491                 const char *soc_elbc_compat = "fsl,p1020-elbc";
 492                 int off = fdt_node_offset_by_compatible(blob, -1,
 493                                 soc_elbc_compat);
 494                 if (off < 0) {
 495                         printf("WARNING: could not find compatible node %s\n",
 496                                soc_elbc_compat);
 497                         return off;
 498                 }
 499                 err = fdt_del_node(blob, off);
 500                 if (err < 0) {
 501                         printf("WARNING: could not remove %s\n",
 502                                soc_elbc_compat);
 503                         return err;
 504                 }
 505                 return 0;
 506         }
 507 #endif
 508
 509 #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
 510 /* Delete USB2 node as it is muxed with eLBC */
 511         usb1_off = fdt_node_offset_by_compatible(blob, -1,
 512                 soc_usb_compat);
 513         if (usb1_off < 0) {
 514                 printf("WARNING: could not find compatible node %s\n",
 515                        soc_usb_compat);
 516                 return usb1_off;
 517         }
 518         usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
 519                         soc_usb_compat);
 520         if (usb2_off < 0) {
 521                 printf("WARNING: could not find compatible node %s\n",
 522                        soc_usb_compat);
 523                 return usb2_off;
 524         }
 525         usb_err = fdt_del_node(blob, usb2_off);
 526         if (usb_err < 0) {
 527                 printf("WARNING: could not remove %s\n", soc_usb_compat);
 528                 return usb_err;
 529         }
 530 #endif
 531
 532         return 0;
 533 }
 534 #endif