board/freescale/p1_p2_rdb_pc/spl_minimal.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation; either version 2 of
   7  * the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12  *
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  *
  20  */
  21
  22 #include <common.h>
  23 #include <ns16550.h>
  24 #include <asm/io.h>
  25 #include <nand.h>
  26 #include <linux/compiler.h>
  27 #include <asm/fsl_law.h>
  28 #include <asm/fsl_ddr_sdram.h>
  29 #include <asm/global_data.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #ifndef CONFIG_SYS_INIT_L2_ADDR
  34 /*
  35  * Fixed sdram init -- doesn't use serial presence detect.
  36  */
  37 static void sdram_init(void)
  38 {
  39         ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
  40
  41         __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
  42         __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
  43 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  44         __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
  45         __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
  46 #endif
  47         __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
  48         __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
  49         __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
  50         __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
  51
  52         __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
  53         __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
  54         __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
  55
  56         __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
  57         __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
  58         __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
  59
  60         __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
  61         __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
  62         __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
  63         __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
  64
  65         /* Set, but do not enable the memory */
  66         __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
  67
  68         asm volatile("sync;isync");
  69         udelay(500);
  70
  71         /* Let the controller go */
  72         out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
  73
  74         set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
  75 }
  76 #endif
  77
  78 void board_init_f(ulong bootflag)
  79 {
  80         u32 plat_ratio;
  81         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  82 #ifndef CONFIG_QE
  83         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  84 #elif defined(CONFIG_P1021RDB)
  85         par_io_t *par_io = (par_io_t *)&(gur->qe_par_io);
  86 #endif
  87
  88         /* initialize selected port with appropriate baud rate */
  89         plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  90         plat_ratio >>= 1;
  91         gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  92
  93         NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  94                         gd->bus_clk / 16 / CONFIG_BAUDRATE);
  95
  96         puts("\nNAND boot... ");
  97
  98 #ifndef CONFIG_QE
  99         /* init DDR3 reset signal */
 100         __raw_writel(0x02000000, &pgpio->gpdir);
 101         __raw_writel(0x00200000, &pgpio->gpodr);
 102         __raw_writel(0x00000000, &pgpio->gpdat);
 103         udelay(1000);
 104         __raw_writel(0x00200000, &pgpio->gpdat);
 105         udelay(1000);
 106         __raw_writel(0x00000000, &pgpio->gpdir);
 107 #elif defined(CONFIG_P1021RDB)
 108         /* init DDR3 reset signal CE_PB8 */
 109         out_be32(&par_io[1].cpdir1, 0x00004000);
 110         out_be32(&par_io[1].cpodr, 0x00800000);
 111         out_be32(&par_io[1].cppar1, 0x00000000);
 112         /* reset DDR3 */
 113         out_be32(&par_io[1].cpdat, 0x00800000);
 114         udelay(1000);
 115         out_be32(&par_io[1].cpdat, 0x00000000);
 116         udelay(1000);
 117         out_be32(&par_io[1].cpdat, 0x00800000);
 118         /* disable the CE_PB8 */
 119         out_be32(&par_io[1].cpdir1, 0x00000000);
 120 #endif
 121
 122 #ifndef CONFIG_SYS_INIT_L2_ADDR
 123         /* Initialize the DDR3 */
 124         sdram_init();
 125 #endif
 126
 127         /* copy code to RAM and jump to it - this should not return */
 128         /* NOTE - code has to be copied out of NAND buffer before
 129          * other blocks can be read.
 130          */
 131         relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
 132 }
 133
 134 void board_init_r(gd_t *gd, ulong dest_addr)
 135 {
 136         nand_boot();
 137 }
 138
 139 void putc(char c)
 140 {
 141         if (c == '\n')
 142                 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
 143
 144         NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
 145 }
 146
 147 void puts(const char *str)
 148 {
 149         while (*str)
 150                 putc(*str++);
 151 }