board/freescale/p2020come/p2020come.c

   1 /*
   2  * Copyright 2009,2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <hwconfig.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/mmu.h>
  12 #include <asm/cache.h>
  13 #include <asm/immap_85xx.h>
  14 #include <asm/mpc85xx_gpio.h>
  15 #include <asm/fsl_serdes.h>
  16 #include <asm/io.h>
  17 #include <miiphy.h>
  18 #include <libfdt.h>
  19 #include <fdt_support.h>
  20 #include <fsl_mdio.h>
  21 #include <tsec.h>
  22 #include <vsc7385.h>
  23 #include <netdev.h>
  24 #include <mmc.h>
  25 #include <malloc.h>
  26 #include <i2c.h>
  27
  28 #if defined(CONFIG_PCI)
  29 #include <asm/fsl_pci.h>
  30 #include <pci.h>
  31 #endif
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #if defined(CONFIG_PCI)
  36 void pci_init_board(void)
  37 {
  38         fsl_pcie_init_board(0);
  39 }
  40
  41 void ft_pci_board_setup(void *blob)
  42 {
  43         FT_FSL_PCI_SETUP;
  44 }
  45 #endif
  46
  47 #define BOARD_PERI_RST_SET      (VSC7385_RST_SET | SLIC_RST_SET | \
  48                                  SGMII_PHY_RST_SET | PCIE_RST_SET | \
  49                                  RGMII_PHY_RST_SET)
  50
  51 #define SYSCLK_MASK     0x00200000
  52 #define BOARDREV_MASK   0x10100000
  53 #define BOARDREV_B      0x10100000
  54 #define BOARDREV_C      0x00100000
  55 #define BOARDREV_D      0x00000000
  56
  57 #define SYSCLK_66       66666666
  58 #define SYSCLK_50       50000000
  59 #define SYSCLK_100      100000000
  60
  61 unsigned long get_board_sys_clk(ulong dummy)
  62 {
  63         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  64         u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
  65
  66         ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  67         switch (ddr_ratio) {
  68         case 0x0C:
  69                 return SYSCLK_66;
  70         case 0x0A:
  71         case 0x08:
  72                 return SYSCLK_100;
  73         default:
  74                 puts("ERROR: unknown DDR ratio\n");
  75                 return SYSCLK_100;
  76         }
  77 }
  78
  79 unsigned long get_board_ddr_clk(ulong dummy)
  80 {
  81         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  82         u32 ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
  83
  84         ddr_ratio >>= MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  85         switch (ddr_ratio) {
  86         case 0x0C:
  87         case 0x0A:
  88                 return SYSCLK_66;
  89         case 0x08:
  90                 return SYSCLK_100;
  91         default:
  92                 puts("ERROR: unknown DDR ratio\n");
  93                 return SYSCLK_100;
  94         }
  95 }
  96
  97 #ifdef CONFIG_MMC
  98 int board_early_init_f(void)
  99 {
 100         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 101
 102         setbits_be32(&gur->pmuxcr,
 103                         (MPC85xx_PMUXCR_SDHC_CD |
 104                          MPC85xx_PMUXCR_SDHC_WP));
 105
 106         /* All the device are enable except for SRIO12 */
 107         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
 108         return 0;
 109 }
 110 #endif
 111
 112 #define GPIO_DIR                0x0f3a0000
 113 #define GPIO_ODR                0x00000000
 114 #define GPIO_DAT                0x001a0000
 115
 116 int checkboard(void)
 117 {
 118         ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xC00);
 119
 120         /*
 121          * GPIO
 122          * 0 - 3: CarryBoard Input;
 123          * 4 - 7: CarryBoard Output;
 124          * 8 : Mux as SDHC_CD (card detection)
 125          * 9 : Mux as SDHC_WP
 126          * 10 : Clear Watchdog timer
 127          * 11 : LED Input
 128          * 12 : Output to 1
 129          * 13 : Open Drain
 130          * 14 : LED Output
 131          * 15 : Switch Input
 132          *
 133          * Set GPIOs 11, 12, 14 to 1.
 134          */
 135         out_be32(&pgpio->gpodr, GPIO_ODR);
 136         mpc85xx_gpio_set(0xffffffff, GPIO_DIR, GPIO_DAT);
 137
 138         puts("Board: Freescale COM Express P2020\n");
 139         return 0;
 140 }
 141
 142 #define M41ST85W_I2C_BUS        1
 143 #define M41ST85W_I2C_ADDR       0x68
 144 #define M41ST85W_ERROR(fmt, args...) printf("ERROR: M41ST85W: " fmt, ##args)
 145
 146 static void m41st85w_clear_bit(u8 reg, u8 mask, const char *name)
 147 {
 148         u8 data;
 149
 150         if (i2c_read(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
 151                 M41ST85W_ERROR("unable to read %s bit\n", name);
 152                 return;
 153         }
 154
 155         if (data & mask) {
 156                 data &= ~mask;
 157                 if (i2c_write(M41ST85W_I2C_ADDR, reg, 1, &data, 1)) {
 158                         M41ST85W_ERROR("unable to clear %s bit\n", name);
 159                         return;
 160                 }
 161         }
 162 }
 163
 164 #define M41ST85W_REG_SEC2       0x01
 165 #define M41ST85W_REG_SEC2_ST    0x80
 166
 167 #define M41ST85W_REG_ALHOUR     0x0c
 168 #define M41ST85W_REG_ALHOUR_HT  0x40
 169
 170 /*
 171  * The P2020COME board has a STMicro M41ST85W RTC/watchdog
 172  * at i2c bus 1 address 0x68.
 173  */
 174 static void start_rtc(void)
 175 {
 176         unsigned int bus = i2c_get_bus_num();
 177
 178         if (i2c_set_bus_num(M41ST85W_I2C_BUS)) {
 179                 M41ST85W_ERROR("unable to set i2c bus\n");
 180                 goto out;
 181         }
 182
 183         /* ensure ST (stop) and HT (halt update) bits are cleared */
 184         m41st85w_clear_bit(M41ST85W_REG_SEC2, M41ST85W_REG_SEC2_ST, "ST");
 185         m41st85w_clear_bit(M41ST85W_REG_ALHOUR, M41ST85W_REG_ALHOUR_HT, "HT");
 186
 187 out:
 188         /* reset the i2c bus */
 189         i2c_set_bus_num(bus);
 190 }
 191
 192 int board_early_init_r(void)
 193 {
 194         start_rtc();
 195         return 0;
 196 }
 197
 198 #define M41ST85W_REG_WATCHDOG           0x09
 199 #define M41ST85W_REG_WATCHDOG_WDS       0x80
 200 #define M41ST85W_REG_WATCHDOG_BMB0      0x04
 201
 202 void board_reset(void)
 203 {
 204         u8 data = M41ST85W_REG_WATCHDOG_WDS | M41ST85W_REG_WATCHDOG_BMB0;
 205
 206         /* set the hardware watchdog timeout to 1/16 second, then hang */
 207         i2c_set_bus_num(M41ST85W_I2C_BUS);
 208         i2c_write(M41ST85W_I2C_ADDR, M41ST85W_REG_WATCHDOG, 1, &data, 1);
 209
 210         while (1)
 211                 /* hang */;
 212 }
 213
 214 #ifdef CONFIG_TSEC_ENET
 215 int board_eth_init(bd_t *bis)
 216 {
 217         struct fsl_pq_mdio_info mdio_info;
 218         struct tsec_info_struct tsec_info[4];
 219         int num = 0;
 220
 221 #ifdef CONFIG_TSEC1
 222         SET_STD_TSEC_INFO(tsec_info[num], 1);
 223         num++;
 224 #endif
 225 #ifdef CONFIG_TSEC2
 226         SET_STD_TSEC_INFO(tsec_info[num], 2);
 227         num++;
 228 #endif
 229 #ifdef CONFIG_TSEC3
 230         SET_STD_TSEC_INFO(tsec_info[num], 3);
 231         if (is_serdes_configured(SGMII_TSEC3)) {
 232                 puts("eTSEC3 is in sgmii mode.");
 233                 tsec_info[num].flags |= TSEC_SGMII;
 234         }
 235         num++;
 236 #endif
 237         if (!num) {
 238                 printf("No TSECs initialized\n");
 239                 return 0;
 240         }
 241
 242         mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
 243         mdio_info.name = DEFAULT_MII_NAME;
 244         fsl_pq_mdio_init(bis, &mdio_info);
 245
 246         tsec_eth_init(bis, tsec_info, num);
 247
 248         return pci_eth_init(bis);
 249 }
 250 #endif
 251
 252 #if defined(CONFIG_OF_BOARD_SETUP)
 253 void ft_board_setup(void *blob, bd_t *bd)
 254 {
 255         phys_addr_t base;
 256         phys_size_t size;
 257
 258         ft_cpu_setup(blob, bd);
 259
 260         base = getenv_bootm_low();
 261         size = getenv_bootm_size();
 262
 263 #if defined(CONFIG_PCI)
 264         ft_pci_board_setup(blob);
 265 #endif
 266
 267         fdt_fixup_memory(blob, (u64)base, (u64)size);
 268
 269 #ifdef CONFIG_HAS_FSL_DR_USB
 270         fdt_fixup_dr_usb(blob, bd);
 271 #endif
 272 }
 273 #endif