2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0
11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h>
15 struct board_specific_parameters
{
17 u32 datarate_mhz_high
;
26 * This table contains all valid speeds we want to override with board
27 * specific parameters. datarate_mhz_high values need to be in ascending order
28 * for each n_ranks group.
30 * ranges for parameters:
35 static const struct board_specific_parameters dimm0
[] = {
38 * num| hi| clk| wrlvl | cpo |wrdata|2T
39 * ranks| mhz|adjst| start | delay|
41 {2, 750, 3, 5, 0xff, 2, 0},
42 {2, 1250, 4, 6, 0xff, 2, 0},
43 {2, 1350, 5, 7, 0xff, 2, 0},
44 {2, 1666, 5, 8, 0xff, 2, 0},
48 void fsl_ddr_board_options(memctl_options_t
*popts
,
50 unsigned int ctrl_num
)
52 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
56 printf("Wrong parameter for controller number %d", ctrl_num
);
65 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
66 * freqency and n_banks specified in board_specific_parameters table.
68 ddr_freq
= get_ddr_freq(0) / 1000000;
69 while (pbsp
->datarate_mhz_high
) {
70 if (pbsp
->n_ranks
== pdimm
->n_ranks
) {
71 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
72 popts
->cpo_override
= pbsp
->cpo
;
73 popts
->write_data_delay
=
74 pbsp
->write_data_delay
;
75 popts
->clk_adjust
= pbsp
->clk_adjust
;
76 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
77 popts
->twot_en
= pbsp
->force_2t
;
86 printf("Error: board specific timing not found "
87 "for data rate %lu MT/s!\n"
88 "Trying to use the highest speed (%u) parameters\n",
89 ddr_freq
, pbsp_highest
->datarate_mhz_high
);
90 popts
->cpo_override
= pbsp_highest
->cpo
;
91 popts
->write_data_delay
= pbsp_highest
->write_data_delay
;
92 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
93 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
94 popts
->twot_en
= pbsp_highest
->force_2t
;
96 panic("DIMM is not supported by this board");
101 * Factors to consider for half-strength driver enable:
102 * - number of DIMMs installed
104 popts
->half_strength_driver_enable
= 0;
105 /* Write leveling override */
106 popts
->wrlvl_override
= 1;
107 popts
->wrlvl_sample
= 0xf;
109 /* Rtt and Rtt_WR override */
110 popts
->rtt_override
= 0;
112 /* Enable ZQ calibration */
115 /* DHC_EN =1, ODT = 60 Ohm */
116 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
;
119 phys_size_t
initdram(void)
121 phys_size_t dram_size
= 0;
123 puts("Initializing....");
127 dram_size
= fsl_ddr_sdram();
129 puts("no SPD and fixed parameters\n");
133 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
134 dram_size
*= 0x100000;