board/freescale/p2041rdb/p2041rdb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011,2012 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <command.h>
   8 #include <env.h>
   9 #include <fdt_support.h>
  10 #include <init.h>
  11 #include <netdev.h>
  12 #include <linux/compiler.h>
  13 #include <asm/mmu.h>
  14 #include <asm/processor.h>
  15 #include <asm/cache.h>
  16 #include <asm/immap_85xx.h>
  17 #include <asm/fsl_law.h>
  18 #include <asm/fsl_serdes.h>
  19 #include <asm/fsl_liodn.h>
  20 #include <fm_eth.h>
  21
  22 extern void pci_of_setup(void *blob, bd_t *bd);
  23
  24 #include "cpld.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 int checkboard(void)
  29 {
  30         u8 sw;
  31         struct cpu_type *cpu = gd->arch.cpu;
  32         unsigned int i;
  33
  34         printf("Board: %sRDB, ", cpu->name);
  35         printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
  36                         CPLD_READ(cpld_ver_sub));
  37
  38         sw = CPLD_READ(fbank_sel);
  39         printf("vBank: %d\n", sw & 0x1);
  40
  41         /*
  42          * Display the actual SERDES reference clocks as configured by the
  43          * dip switches on the board.  Note that the SWx registers could
  44          * technically be set to force the reference clocks to match the
  45          * values that the SERDES expects (or vice versa).  For now, however,
  46          * we just display both values and hope the user notices when they
  47          * don't match.
  48          */
  49         puts("SERDES Reference Clocks: ");
  50         sw = in_8(&CPLD_SW(2)) >> 2;
  51         for (i = 0; i < 2; i++) {
  52                 static const char * const freq[][3] = {{"0", "100", "125"},
  53                                                 {"100", "156.25", "125"}
  54                 };
  55                 unsigned int clock = (sw >> (2 * i)) & 3;
  56
  57                 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
  58         }
  59         puts("\n");
  60
  61         return 0;
  62 }
  63
  64 int board_early_init_f(void)
  65 {
  66         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  67
  68         /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
  69         setbits_be32(&gur->ddrclkdr, 0x000f000f);
  70
  71         return 0;
  72 }
  73
  74 #define CPLD_LANE_A_SEL 0x1
  75 #define CPLD_LANE_G_SEL 0x2
  76 #define CPLD_LANE_C_SEL 0x4
  77 #define CPLD_LANE_D_SEL 0x8
  78
  79 void board_config_lanes_mux(void)
  80 {
  81         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  82         int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
  83                                 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  84
  85         u8 mux = 0;
  86         switch (srds_prtcl) {
  87         case 0x2:
  88         case 0x5:
  89         case 0x9:
  90         case 0xa:
  91         case 0xf:
  92                 break;
  93         case 0x8:
  94                 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
  95                 break;
  96         case 0x14:
  97                 mux |= CPLD_LANE_A_SEL;
  98                 break;
  99         case 0x17:
 100                 mux |= CPLD_LANE_G_SEL;
 101                 break;
 102         case 0x16:
 103         case 0x19:
 104         case 0x1a:
 105                 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
 106                 break;
 107         case 0x1c:
 108                 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
 109                 break;
 110         default:
 111                 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
 112                 break;
 113         }
 114         CPLD_WRITE(serdes_mux, mux);
 115 }
 116
 117 int board_early_init_r(void)
 118 {
 119         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 120         int flash_esel = find_tlb_idx((void *)flashbase, 1);
 121
 122         /*
 123          * Remap Boot flash + PROMJET region to caching-inhibited
 124          * so that flash can be erased properly.
 125          */
 126
 127         /* Flush d-cache and invalidate i-cache of any FLASH data */
 128         flush_dcache();
 129         invalidate_icache();
 130
 131         if (flash_esel == -1) {
 132                 /* very unlikely unless something is messed up */
 133                 puts("Error: Could not find TLB for FLASH BASE\n");
 134                 flash_esel = 2; /* give our best effort to continue */
 135         } else {
 136                 /* invalidate existing TLB entry for flash + promjet */
 137                 disable_tlb(flash_esel);
 138         }
 139
 140         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 141                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 142                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 143
 144         board_config_lanes_mux();
 145
 146         return 0;
 147 }
 148
 149 unsigned long get_board_sys_clk(unsigned long dummy)
 150 {
 151         u8 sysclk_conf = CPLD_READ(sysclk_sw1);
 152
 153         switch (sysclk_conf & 0x7) {
 154         case CPLD_SYSCLK_83:
 155                 return 83333333;
 156         case CPLD_SYSCLK_100:
 157                 return 100000000;
 158         default:
 159                 return 66666666;
 160         }
 161 }
 162
 163 #define NUM_SRDS_BANKS  2
 164
 165 int misc_init_r(void)
 166 {
 167         serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 168         u32 actual[NUM_SRDS_BANKS];
 169         unsigned int i;
 170         u8 sw;
 171         static const int freq[][3] = {
 172                 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
 173                 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
 174                         SRDS_PLLCR0_RFCK_SEL_125}
 175         };
 176
 177         sw = in_8(&CPLD_SW(2)) >> 2;
 178         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 179                 unsigned int clock = (sw >> (2 * i)) & 3;
 180                 if (clock == 0x3) {
 181                         printf("Warning: SDREFCLK%u switch setting of '11' is "
 182                                "unsupported\n", i + 1);
 183                         break;
 184                 }
 185                 if (i == 0 && clock == 0)
 186                         puts("Warning: SDREFCLK1 switch setting of"
 187                                 "'00' is unsupported\n");
 188                 else
 189                         actual[i] = freq[i][clock];
 190
 191                 /*
 192                  * PC board uses a different CPLD with PB board, this CPLD
 193                  * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
 194                  * board has cpld_ver_sub = 0, and pcba_ver = 4.
 195                  */
 196                 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
 197                     (CPLD_READ(pcba_ver) == 5)) {
 198                         /* PC board bank2 frequency */
 199                         actual[i] = freq[i-1][clock];
 200                 }
 201         }
 202
 203         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 204                 u32 expected = in_be32(&regs->bank[i].pllcr0);
 205                 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
 206                 if (expected != actual[i]) {
 207                         printf("Warning: SERDES bank %u expects reference clock"
 208                                " %sMHz, but actual is %sMHz\n", i + 1,
 209                                serdes_clock_to_string(expected),
 210                                serdes_clock_to_string(actual[i]));
 211                 }
 212         }
 213
 214         return 0;
 215 }
 216
 217 int ft_board_setup(void *blob, bd_t *bd)
 218 {
 219         phys_addr_t base;
 220         phys_size_t size;
 221
 222         ft_cpu_setup(blob, bd);
 223
 224         base = env_get_bootm_low();
 225         size = env_get_bootm_size();
 226
 227         fdt_fixup_memory(blob, (u64)base, (u64)size);
 228
 229 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 230         fsl_fdt_fixup_dr_usb(blob, bd);
 231 #endif
 232
 233 #ifdef CONFIG_PCI
 234         pci_of_setup(blob, bd);
 235 #endif
 236
 237         fdt_fixup_liodn(blob);
 238 #ifdef CONFIG_SYS_DPAA_FMAN
 239         fdt_fixup_fman_ethernet(blob);
 240 #endif
 241
 242         return 0;
 243 }