board/freescale/p2041rdb/p2041rdb.c

   1 /*
   2  * Copyright 2011,2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <netdev.h>
  10 #include <linux/compiler.h>
  11 #include <asm/mmu.h>
  12 #include <asm/processor.h>
  13 #include <asm/cache.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <fm_eth.h>
  20
  21 extern void pci_of_setup(void *blob, bd_t *bd);
  22
  23 #include "cpld.h"
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 int checkboard(void)
  28 {
  29         u8 sw;
  30         struct cpu_type *cpu = gd->arch.cpu;
  31         unsigned int i;
  32
  33         printf("Board: %sRDB, ", cpu->name);
  34         printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
  35                         CPLD_READ(cpld_ver_sub));
  36
  37         sw = CPLD_READ(fbank_sel);
  38         printf("vBank: %d\n", sw & 0x1);
  39
  40         /*
  41          * Display the actual SERDES reference clocks as configured by the
  42          * dip switches on the board.  Note that the SWx registers could
  43          * technically be set to force the reference clocks to match the
  44          * values that the SERDES expects (or vice versa).  For now, however,
  45          * we just display both values and hope the user notices when they
  46          * don't match.
  47          */
  48         puts("SERDES Reference Clocks: ");
  49         sw = in_8(&CPLD_SW(2)) >> 2;
  50         for (i = 0; i < 2; i++) {
  51                 static const char * const freq[][3] = {{"0", "100", "125"},
  52                                                 {"100", "156.25", "125"}
  53                 };
  54                 unsigned int clock = (sw >> (2 * i)) & 3;
  55
  56                 printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
  57         }
  58         puts("\n");
  59
  60         return 0;
  61 }
  62
  63 int board_early_init_f(void)
  64 {
  65         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  66
  67         /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
  68         setbits_be32(&gur->ddrclkdr, 0x000f000f);
  69
  70         return 0;
  71 }
  72
  73 #define CPLD_LANE_A_SEL 0x1
  74 #define CPLD_LANE_G_SEL 0x2
  75 #define CPLD_LANE_C_SEL 0x4
  76 #define CPLD_LANE_D_SEL 0x8
  77
  78 void board_config_lanes_mux(void)
  79 {
  80         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  81         int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
  82                                 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
  83
  84         u8 mux = 0;
  85         switch (srds_prtcl) {
  86         case 0x2:
  87         case 0x5:
  88         case 0x9:
  89         case 0xa:
  90         case 0xf:
  91                 break;
  92         case 0x8:
  93                 mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
  94                 break;
  95         case 0x14:
  96                 mux |= CPLD_LANE_A_SEL;
  97                 break;
  98         case 0x17:
  99                 mux |= CPLD_LANE_G_SEL;
 100                 break;
 101         case 0x16:
 102         case 0x19:
 103         case 0x1a:
 104                 mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
 105                 break;
 106         case 0x1c:
 107                 mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
 108                 break;
 109         default:
 110                 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
 111                 break;
 112         }
 113         CPLD_WRITE(serdes_mux, mux);
 114 }
 115
 116 int board_early_init_r(void)
 117 {
 118         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 119         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 120
 121         /*
 122          * Remap Boot flash + PROMJET region to caching-inhibited
 123          * so that flash can be erased properly.
 124          */
 125
 126         /* Flush d-cache and invalidate i-cache of any FLASH data */
 127         flush_dcache();
 128         invalidate_icache();
 129
 130         /* invalidate existing TLB entry for flash + promjet */
 131         disable_tlb(flash_esel);
 132
 133         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 134                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 135                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 136
 137         set_liodns();
 138         setup_portals();
 139         board_config_lanes_mux();
 140
 141         return 0;
 142 }
 143
 144 unsigned long get_board_sys_clk(unsigned long dummy)
 145 {
 146         u8 sysclk_conf = CPLD_READ(sysclk_sw1);
 147
 148         switch (sysclk_conf & 0x7) {
 149         case CPLD_SYSCLK_83:
 150                 return 83333333;
 151         case CPLD_SYSCLK_100:
 152                 return 100000000;
 153         default:
 154                 return 66666666;
 155         }
 156 }
 157
 158 static const char *serdes_clock_to_string(u32 clock)
 159 {
 160         switch (clock) {
 161         case SRDS_PLLCR0_RFCK_SEL_100:
 162                 return "100";
 163         case SRDS_PLLCR0_RFCK_SEL_125:
 164                 return "125";
 165         case SRDS_PLLCR0_RFCK_SEL_156_25:
 166                 return "156.25";
 167         default:
 168                 return "150";
 169         }
 170 }
 171
 172 #define NUM_SRDS_BANKS  2
 173
 174 int misc_init_r(void)
 175 {
 176         serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 177         u32 actual[NUM_SRDS_BANKS];
 178         unsigned int i;
 179         u8 sw;
 180         static const int freq[][3] = {
 181                 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
 182                 {SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
 183                         SRDS_PLLCR0_RFCK_SEL_125}
 184         };
 185
 186         sw = in_8(&CPLD_SW(2)) >> 2;
 187         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 188                 unsigned int clock = (sw >> (2 * i)) & 3;
 189                 if (clock == 0x3) {
 190                         printf("Warning: SDREFCLK%u switch setting of '11' is "
 191                                "unsupported\n", i + 1);
 192                         break;
 193                 }
 194                 if (i == 0 && clock == 0)
 195                         puts("Warning: SDREFCLK1 switch setting of"
 196                                 "'00' is unsupported\n");
 197                 else
 198                         actual[i] = freq[i][clock];
 199
 200                 /*
 201                  * PC board uses a different CPLD with PB board, this CPLD
 202                  * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
 203                  * board has cpld_ver_sub = 0, and pcba_ver = 4.
 204                  */
 205                 if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
 206                     (CPLD_READ(pcba_ver) == 5)) {
 207                         /* PC board bank2 frequency */
 208                         actual[i] = freq[i-1][clock];
 209                 }
 210         }
 211
 212         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 213                 u32 expected = in_be32(&regs->bank[i].pllcr0);
 214                 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
 215                 if (expected != actual[i]) {
 216                         printf("Warning: SERDES bank %u expects reference clock"
 217                                " %sMHz, but actual is %sMHz\n", i + 1,
 218                                serdes_clock_to_string(expected),
 219                                serdes_clock_to_string(actual[i]));
 220                 }
 221         }
 222
 223         return 0;
 224 }
 225
 226 void ft_board_setup(void *blob, bd_t *bd)
 227 {
 228         phys_addr_t base;
 229         phys_size_t size;
 230
 231         ft_cpu_setup(blob, bd);
 232
 233         base = getenv_bootm_low();
 234         size = getenv_bootm_size();
 235
 236         fdt_fixup_memory(blob, (u64)base, (u64)size);
 237
 238 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 239         fdt_fixup_dr_usb(blob, bd);
 240 #endif
 241
 242 #ifdef CONFIG_PCI
 243         pci_of_setup(blob, bd);
 244 #endif
 245
 246         fdt_fixup_liodn(blob);
 247 #ifdef CONFIG_SYS_DPAA_FMAN
 248         fdt_fixup_fman_ethernet(blob);
 249 #endif
 250 }