2 * Copyright 2011,2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/compiler.h>
12 #include <asm/processor.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_liodn.h>
20 extern void pci_of_setup(void *blob
, bd_t
*bd
);
24 DECLARE_GLOBAL_DATA_PTR
;
29 struct cpu_type
*cpu
= gd
->arch
.cpu
;
32 printf("Board: %sRDB, ", cpu
->name
);
33 printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver
),
34 CPLD_READ(cpld_ver_sub
));
36 sw
= CPLD_READ(fbank_sel
);
37 printf("vBank: %d\n", sw
& 0x1);
40 * Display the actual SERDES reference clocks as configured by the
41 * dip switches on the board. Note that the SWx registers could
42 * technically be set to force the reference clocks to match the
43 * values that the SERDES expects (or vice versa). For now, however,
44 * we just display both values and hope the user notices when they
47 puts("SERDES Reference Clocks: ");
48 sw
= in_8(&CPLD_SW(2)) >> 2;
49 for (i
= 0; i
< 2; i
++) {
50 static const char * const freq
[][3] = {{"0", "100", "125"},
51 {"100", "156.25", "125"}
53 unsigned int clock
= (sw
>> (2 * i
)) & 3;
55 printf("Bank%u=%sMhz ", i
+1, freq
[i
][clock
]);
62 int board_early_init_f(void)
64 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
66 /* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
67 setbits_be32(&gur
->ddrclkdr
, 0x000f000f);
72 #define CPLD_LANE_A_SEL 0x1
73 #define CPLD_LANE_G_SEL 0x2
74 #define CPLD_LANE_C_SEL 0x4
75 #define CPLD_LANE_D_SEL 0x8
77 void board_config_lanes_mux(void)
79 ccsr_gur_t
*gur
= (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR
;
80 int srds_prtcl
= (in_be32(&gur
->rcwsr
[4]) &
81 FSL_CORENET_RCWSR4_SRDS_PRTCL
) >> 26;
92 mux
|= CPLD_LANE_C_SEL
| CPLD_LANE_D_SEL
;
95 mux
|= CPLD_LANE_A_SEL
;
98 mux
|= CPLD_LANE_G_SEL
;
103 mux
|= CPLD_LANE_G_SEL
| CPLD_LANE_C_SEL
| CPLD_LANE_D_SEL
;
106 mux
|= CPLD_LANE_G_SEL
| CPLD_LANE_A_SEL
;
109 printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl
);
112 CPLD_WRITE(serdes_mux
, mux
);
115 int board_early_init_r(void)
117 const unsigned int flashbase
= CONFIG_SYS_FLASH_BASE
;
118 int flash_esel
= find_tlb_idx((void *)flashbase
, 1);
121 * Remap Boot flash + PROMJET region to caching-inhibited
122 * so that flash can be erased properly.
125 /* Flush d-cache and invalidate i-cache of any FLASH data */
129 if (flash_esel
== -1) {
130 /* very unlikely unless something is messed up */
131 puts("Error: Could not find TLB for FLASH BASE\n");
132 flash_esel
= 2; /* give our best effort to continue */
134 /* invalidate existing TLB entry for flash + promjet */
135 disable_tlb(flash_esel
);
138 set_tlb(1, flashbase
, CONFIG_SYS_FLASH_BASE_PHYS
,
139 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
140 0, flash_esel
, BOOKE_PAGESZ_256M
, 1);
142 board_config_lanes_mux();
147 unsigned long get_board_sys_clk(unsigned long dummy
)
149 u8 sysclk_conf
= CPLD_READ(sysclk_sw1
);
151 switch (sysclk_conf
& 0x7) {
154 case CPLD_SYSCLK_100
:
161 #define NUM_SRDS_BANKS 2
163 int misc_init_r(void)
165 serdes_corenet_t
*regs
= (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR
;
166 u32 actual
[NUM_SRDS_BANKS
];
169 static const int freq
[][3] = {
170 {0, SRDS_PLLCR0_RFCK_SEL_100
, SRDS_PLLCR0_RFCK_SEL_125
},
171 {SRDS_PLLCR0_RFCK_SEL_100
, SRDS_PLLCR0_RFCK_SEL_156_25
,
172 SRDS_PLLCR0_RFCK_SEL_125
}
175 sw
= in_8(&CPLD_SW(2)) >> 2;
176 for (i
= 0; i
< NUM_SRDS_BANKS
; i
++) {
177 unsigned int clock
= (sw
>> (2 * i
)) & 3;
179 printf("Warning: SDREFCLK%u switch setting of '11' is "
180 "unsupported\n", i
+ 1);
183 if (i
== 0 && clock
== 0)
184 puts("Warning: SDREFCLK1 switch setting of"
185 "'00' is unsupported\n");
187 actual
[i
] = freq
[i
][clock
];
190 * PC board uses a different CPLD with PB board, this CPLD
191 * has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
192 * board has cpld_ver_sub = 0, and pcba_ver = 4.
194 if ((i
== 1) && (CPLD_READ(cpld_ver_sub
) == 1) &&
195 (CPLD_READ(pcba_ver
) == 5)) {
196 /* PC board bank2 frequency */
197 actual
[i
] = freq
[i
-1][clock
];
201 for (i
= 0; i
< NUM_SRDS_BANKS
; i
++) {
202 u32 expected
= in_be32(®s
->bank
[i
].pllcr0
);
203 expected
&= SRDS_PLLCR0_RFCK_SEL_MASK
;
204 if (expected
!= actual
[i
]) {
205 printf("Warning: SERDES bank %u expects reference clock"
206 " %sMHz, but actual is %sMHz\n", i
+ 1,
207 serdes_clock_to_string(expected
),
208 serdes_clock_to_string(actual
[i
]));
215 int ft_board_setup(void *blob
, bd_t
*bd
)
220 ft_cpu_setup(blob
, bd
);
222 base
= getenv_bootm_low();
223 size
= getenv_bootm_size();
225 fdt_fixup_memory(blob
, (u64
)base
, (u64
)size
);
227 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
228 fsl_fdt_fixup_dr_usb(blob
, bd
);
232 pci_of_setup(blob
, bd
);
235 fdt_fixup_liodn(blob
);
236 #ifdef CONFIG_SYS_DPAA_FMAN
237 fdt_fixup_fman_ethernet(blob
);