1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014 Freescale Semiconductor, Inc.
5 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
12 #include <asm/processor.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_law.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/fsl_portals.h>
17 #include <asm/fsl_liodn.h>
23 #include <fsl_dtsec.h>
24 #include <asm/fsl_serdes.h>
25 #include "../common/qixis.h"
26 #include "../common/fman.h"
27 #include "t102xqds_qixis.h"
29 #define EMI_NONE 0xFFFFFFFF
39 static int mdio_mux
[NUM_FM_PORTS
];
41 static const char * const mdio_names
[] = {
42 "T1024QDS_MDIO_RGMII1",
43 "T1024QDS_MDIO_RGMII2",
44 "T1024QDS_MDIO_SLOT1",
45 "T1024QDS_MDIO_SLOT2",
46 "T1024QDS_MDIO_SLOT3",
47 "T1024QDS_MDIO_SLOT4",
48 "T1024QDS_MDIO_SLOT5",
53 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
54 static u8 lane_to_slot
[] = {2, 3, 4, 5};
56 static const char *t1024qds_mdio_name_for_muxval(u8 muxval
)
58 return mdio_names
[muxval
];
61 struct mii_dev
*mii_dev_for_muxval(u8 muxval
)
69 name
= t1024qds_mdio_name_for_muxval(muxval
);
72 printf("No bus for muxval %x\n", muxval
);
76 bus
= miiphy_get_dev_by_name(name
);
79 printf("No bus by name %s\n", name
);
86 struct t1024qds_mdio
{
88 struct mii_dev
*realbus
;
91 static void t1024qds_mux_mdio(u8 muxval
)
96 brdcfg4
= QIXIS_READ(brdcfg
[4]);
97 brdcfg4
&= ~BRDCFG4_EMISEL_MASK
;
98 brdcfg4
|= (muxval
<< BRDCFG4_EMISEL_SHIFT
);
99 QIXIS_WRITE(brdcfg
[4], brdcfg4
);
103 static int t1024qds_mdio_read(struct mii_dev
*bus
, int addr
, int devad
,
106 struct t1024qds_mdio
*priv
= bus
->priv
;
108 t1024qds_mux_mdio(priv
->muxval
);
110 return priv
->realbus
->read(priv
->realbus
, addr
, devad
, regnum
);
113 static int t1024qds_mdio_write(struct mii_dev
*bus
, int addr
, int devad
,
114 int regnum
, u16 value
)
116 struct t1024qds_mdio
*priv
= bus
->priv
;
118 t1024qds_mux_mdio(priv
->muxval
);
120 return priv
->realbus
->write(priv
->realbus
, addr
, devad
, regnum
, value
);
123 static int t1024qds_mdio_reset(struct mii_dev
*bus
)
125 struct t1024qds_mdio
*priv
= bus
->priv
;
127 return priv
->realbus
->reset(priv
->realbus
);
130 static int t1024qds_mdio_init(char *realbusname
, u8 muxval
)
132 struct t1024qds_mdio
*pmdio
;
133 struct mii_dev
*bus
= mdio_alloc();
136 printf("Failed to allocate t1024qds MDIO bus\n");
140 pmdio
= malloc(sizeof(*pmdio
));
142 printf("Failed to allocate t1024qds private data\n");
147 bus
->read
= t1024qds_mdio_read
;
148 bus
->write
= t1024qds_mdio_write
;
149 bus
->reset
= t1024qds_mdio_reset
;
150 strcpy(bus
->name
, t1024qds_mdio_name_for_muxval(muxval
));
152 pmdio
->realbus
= miiphy_get_dev_by_name(realbusname
);
154 if (!pmdio
->realbus
) {
155 printf("No bus with name %s\n", realbusname
);
161 pmdio
->muxval
= muxval
;
163 return mdio_register(bus
);
166 void board_ft_fman_fixup_port(void *fdt
, char *compat
, phys_addr_t addr
,
167 enum fm_port port
, int offset
)
169 struct fixed_link f_link
;
171 if (fm_info_get_enet_if(port
) == PHY_INTERFACE_MODE_RGMII
) {
172 if (port
== FM1_DTSEC3
) {
173 fdt_set_phy_handle(fdt
, compat
, addr
, "rgmii_phy2");
174 fdt_setprop_string(fdt
, offset
, "phy-connection-type",
176 fdt_status_okay_by_alias(fdt
, "emi1_rgmii1");
178 } else if (fm_info_get_enet_if(port
) == PHY_INTERFACE_MODE_SGMII
) {
179 if (port
== FM1_DTSEC1
) {
180 fdt_set_phy_handle(fdt
, compat
, addr
,
181 "sgmii_vsc8234_phy_s5");
182 } else if (port
== FM1_DTSEC2
) {
183 fdt_set_phy_handle(fdt
, compat
, addr
,
184 "sgmii_vsc8234_phy_s4");
186 } else if (fm_info_get_enet_if(port
) == PHY_INTERFACE_MODE_SGMII_2500
) {
187 if (port
== FM1_DTSEC3
) {
188 fdt_set_phy_handle(fdt
, compat
, addr
,
189 "sgmii_aqr105_phy_s3");
191 } else if (fm_info_get_enet_if(port
) == PHY_INTERFACE_MODE_QSGMII
) {
194 fdt_set_phy_handle(fdt
, compat
, addr
, "qsgmii_phy_p1");
197 fdt_set_phy_handle(fdt
, compat
, addr
, "qsgmii_phy_p2");
200 fdt_set_phy_handle(fdt
, compat
, addr
, "qsgmii_phy_p3");
203 fdt_set_phy_handle(fdt
, compat
, addr
, "qsgmii_phy_p4");
208 fdt_delprop(fdt
, offset
, "phy-connection-type");
209 fdt_setprop_string(fdt
, offset
, "phy-connection-type",
211 fdt_status_okay_by_alias(fdt
, "emi1_slot2");
212 } else if (fm_info_get_enet_if(port
) == PHY_INTERFACE_MODE_XGMII
) {
214 f_link
.phy_id
= port
;
216 f_link
.link_speed
= 10000;
218 f_link
.asym_pause
= 0;
220 fdt_delprop(fdt
, offset
, "phy-handle");
221 fdt_setprop(fdt
, offset
, "fixed-link", &f_link
, sizeof(f_link
));
222 fdt_setprop_string(fdt
, offset
, "phy-connection-type", "xgmii");
226 void fdt_fixup_board_enet(void *fdt
)
231 * This function reads RCW to check if Serdes1{A:D} is configured
232 * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
234 static void initialize_lane_to_slot(void)
236 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
237 u32 srds_s1
= in_be32(&gur
->rcwsr
[4]) &
238 FSL_CORENET2_RCWSR4_SRDS1_PRTCL
;
240 srds_s1
>>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT
;
252 int board_eth_init(bd_t
*bis
)
254 #if defined(CONFIG_FMAN_ENET)
255 int i
, idx
, lane
, slot
, interface
;
256 struct memac_mdio_info dtsec_mdio_info
;
257 struct memac_mdio_info tgec_mdio_info
;
258 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
261 srds_s1
= in_be32(&gur
->rcwsr
[4]) &
262 FSL_CORENET2_RCWSR4_SRDS1_PRTCL
;
263 srds_s1
>>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT
;
265 initialize_lane_to_slot();
267 /* Initialize the mdio_mux array so we can recognize empty elements */
268 for (i
= 0; i
< NUM_FM_PORTS
; i
++)
269 mdio_mux
[i
] = EMI_NONE
;
271 dtsec_mdio_info
.regs
=
272 (struct memac_mdio_controller
*)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR
;
274 dtsec_mdio_info
.name
= DEFAULT_FM_MDIO_NAME
;
276 /* Register the 1G MDIO bus */
277 fm_memac_mdio_init(bis
, &dtsec_mdio_info
);
279 tgec_mdio_info
.regs
=
280 (struct memac_mdio_controller
*)CONFIG_SYS_FM1_TGEC_MDIO_ADDR
;
281 tgec_mdio_info
.name
= DEFAULT_FM_TGEC_MDIO_NAME
;
283 /* Register the 10G MDIO bus */
284 fm_memac_mdio_init(bis
, &tgec_mdio_info
);
286 /* Register the muxing front-ends to the MDIO buses */
287 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_RGMII1
);
288 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_RGMII2
);
289 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT1
);
290 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT2
);
291 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT3
);
292 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT4
);
293 t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT5
);
294 t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME
, EMI2
);
296 /* Set the two on-board RGMII PHY address */
297 fm_info_set_phy_address(FM1_DTSEC3
, RGMII_PHY2_ADDR
);
298 fm_info_set_phy_address(FM1_DTSEC4
, RGMII_PHY1_ADDR
);
303 /* QSGMII in Slot2 */
304 fm_info_set_phy_address(FM1_DTSEC1
, 0x8);
305 fm_info_set_phy_address(FM1_DTSEC2
, 0x9);
306 fm_info_set_phy_address(FM1_DTSEC3
, 0xa);
307 fm_info_set_phy_address(FM1_DTSEC4
, 0xb);
312 * XFI does not need a PHY to work, but to avoid U-Boot use
313 * default PHY address which is zero to a MAC when it found
314 * a MAC has no PHY address, we give a PHY address to XFI
315 * MAC, and should not use a real XAUI PHY address, since
316 * MDIO can access it successfully, and then MDIO thinks the
317 * XAUI card is used for the XFI MAC, which will cause error.
319 fm_info_set_phy_address(FM1_10GEC1
, 4);
320 fm_info_set_phy_address(FM1_DTSEC2
, SGMII_CARD_PORT1_PHY_ADDR
);
323 /* SGMII in Slot3, Slot4, Slot5 */
324 fm_info_set_phy_address(FM1_DTSEC1
, SGMII_CARD_AQ_PHY_ADDR_S5
);
325 fm_info_set_phy_address(FM1_DTSEC2
, SGMII_CARD_AQ_PHY_ADDR_S4
);
326 fm_info_set_phy_address(FM1_DTSEC3
, SGMII_CARD_PORT1_PHY_ADDR
);
329 fm_info_set_phy_address(FM1_DTSEC1
, SGMII_CARD_AQ_PHY_ADDR_S5
);
330 fm_info_set_phy_address(FM1_DTSEC2
, SGMII_CARD_AQ_PHY_ADDR_S4
);
331 fm_info_set_phy_address(FM1_DTSEC3
, SGMII_CARD_AQ_PHY_ADDR_S3
);
334 fm_info_set_phy_address(FM1_DTSEC1
, SGMII_CARD_PORT1_PHY_ADDR
);
337 fm_info_set_phy_address(FM1_DTSEC1
, SGMII_CARD_PORT1_PHY_ADDR
);
338 fm_info_set_phy_address(FM1_DTSEC3
, SGMII_CARD_AQ_PHY_ADDR_S3
);
341 fm_info_set_phy_address(FM1_DTSEC2
, SGMII_CARD_PORT1_PHY_ADDR
);
344 fm_info_set_phy_address(FM1_DTSEC2
, SGMII_CARD_PORT1_PHY_ADDR
);
345 fm_info_set_phy_address(FM1_DTSEC3
, SGMII_CARD_PORT1_PHY_ADDR
);
348 fm_info_set_phy_address(FM1_DTSEC1
, SGMII_CARD_PORT1_PHY_ADDR
);
349 fm_info_set_phy_address(FM1_DTSEC2
, SGMII_CARD_PORT1_PHY_ADDR
);
352 fm_info_set_phy_address(FM1_DTSEC1
, SGMII_CARD_PORT1_PHY_ADDR
);
353 fm_info_set_phy_address(FM1_DTSEC2
, SGMII_CARD_PORT1_PHY_ADDR
);
354 fm_info_set_phy_address(FM1_DTSEC3
, SGMII_CARD_PORT1_PHY_ADDR
);
360 for (i
= FM1_DTSEC1
; i
< FM1_DTSEC1
+ CONFIG_SYS_NUM_FM1_DTSEC
; i
++) {
361 idx
= i
- FM1_DTSEC1
;
362 interface
= fm_info_get_enet_if(i
);
364 case PHY_INTERFACE_MODE_SGMII
:
365 case PHY_INTERFACE_MODE_SGMII_2500
:
366 case PHY_INTERFACE_MODE_QSGMII
:
367 if (interface
== PHY_INTERFACE_MODE_SGMII
) {
368 lane
= serdes_get_first_lane(FSL_SRDS_1
,
369 SGMII_FM1_DTSEC1
+ idx
);
370 } else if (interface
== PHY_INTERFACE_MODE_SGMII_2500
) {
371 lane
= serdes_get_first_lane(FSL_SRDS_1
,
372 SGMII_2500_FM1_DTSEC1
+ idx
);
374 lane
= serdes_get_first_lane(FSL_SRDS_1
,
381 slot
= lane_to_slot
[lane
];
382 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
384 if (QIXIS_READ(present2
) & (1 << (slot
- 1)))
389 mdio_mux
[i
] = EMI1_SLOT2
;
390 fm_info_set_mdio(i
, mii_dev_for_muxval(
394 mdio_mux
[i
] = EMI1_SLOT3
;
395 fm_info_set_mdio(i
, mii_dev_for_muxval(
399 mdio_mux
[i
] = EMI1_SLOT4
;
400 fm_info_set_mdio(i
, mii_dev_for_muxval(
404 mdio_mux
[i
] = EMI1_SLOT5
;
405 fm_info_set_mdio(i
, mii_dev_for_muxval(
410 case PHY_INTERFACE_MODE_RGMII
:
412 mdio_mux
[i
] = EMI1_RGMII2
;
413 else if (i
== FM1_DTSEC4
)
414 mdio_mux
[i
] = EMI1_RGMII1
;
415 fm_info_set_mdio(i
, mii_dev_for_muxval(mdio_mux
[i
]));
422 for (i
= FM1_10GEC1
; i
< FM1_10GEC1
+ CONFIG_SYS_NUM_FM1_10GEC
; i
++) {
423 idx
= i
- FM1_10GEC1
;
424 switch (fm_info_get_enet_if(i
)) {
425 case PHY_INTERFACE_MODE_XGMII
:
426 lane
= serdes_get_first_lane(FSL_SRDS_1
,
431 fm_info_set_mdio(i
, mii_dev_for_muxval(mdio_mux
[i
]));
439 #endif /* CONFIG_FMAN_ENET */
441 return pci_eth_init(bis
);