board/freescale/t102xqds/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/mmu.h>
   8
   9 struct fsl_e_tlb_entry tlb_table[] = {
  10         /* TLB 0 - for temp stack in cache */
  11         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  12                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  13                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  14                       0, 0, BOOKE_PAGESZ_4K, 0),
  15         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  16                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  17                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  18                       0, 0, BOOKE_PAGESZ_4K, 0),
  19         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  20                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  21                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  25                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26                       0, 0, BOOKE_PAGESZ_4K, 0),
  27
  28         /* TLB 1 */
  29         /* *I*** - Covers boot page */
  30 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  31         /*
  32          * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
  33          * SRAM is at 0xfffc0000, it covered the 0xfffff000.
  34          */
  35         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  36                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  37                       0, 0, BOOKE_PAGESZ_256K, 1),
  38 #else
  39         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  40                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  41                       0, 0, BOOKE_PAGESZ_4K, 1),
  42 #endif
  43
  44         /* *I*G* - CCSRBAR */
  45         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  46                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  47                       0, 1, BOOKE_PAGESZ_16M, 1),
  48
  49         /* *I*G* - Flash, localbus */
  50         /* This will be changed to *I*G* after relocation to RAM. */
  51         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  52                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  53                       0, 2, BOOKE_PAGESZ_256M, 1),
  54
  55 #ifndef CONFIG_SPL_BUILD
  56         /* *I*G* - PCI */
  57         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  58                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  59                       0, 3, BOOKE_PAGESZ_1G, 1),
  60
  61         /* *I*G* - PCI I/O */
  62         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  63                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  64                       0, 4, BOOKE_PAGESZ_256K, 1),
  65
  66         /* Bman/Qman */
  67 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  68         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  69                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  70                       0, 5, BOOKE_PAGESZ_16M, 1),
  71         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  72                       CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  73                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  74                       0, 6, BOOKE_PAGESZ_16M, 1),
  75 #endif
  76 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  77         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  78                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  79                       0, 7, BOOKE_PAGESZ_16M, 1),
  80         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  81                       CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  82                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  83                       0, 8, BOOKE_PAGESZ_16M, 1),
  84 #endif
  85 #endif
  86 #ifdef CONFIG_SYS_DCSRBAR_PHYS
  87         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  88                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  89                       0, 9, BOOKE_PAGESZ_4M, 1),
  90 #endif
  91 #ifdef CONFIG_SYS_NAND_BASE
  92         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  93                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  94                       0, 10, BOOKE_PAGESZ_64K, 1),
  95 #endif
  96 #ifdef QIXIS_BASE
  97         SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
  98                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  99                       0, 11, BOOKE_PAGESZ_4K, 1),
 100 #endif
 101
 102 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 103         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 104                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 105                       0, 12, BOOKE_PAGESZ_1G, 1),
 106         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 107                       CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 108                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
 109                       0, 13, BOOKE_PAGESZ_1G, 1)
 110 #endif
 111         /* entry 14 and 15 has been used hard coded, they will be disabled
 112          * in cpu_init_f, so if needed more, will use entry 16 later.
 113          */
 114 };
 115
 116 int num_tlb_entries = ARRAY_SIZE(tlb_table);