2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 struct fsl_e_tlb_entry tlb_table
[] = {
11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
,
13 CONFIG_SYS_INIT_RAM_ADDR_PHYS
,
14 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
15 0, 0, BOOKE_PAGESZ_4K
, 0),
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 4 * 1024,
17 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 4 * 1024,
18 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
19 0, 0, BOOKE_PAGESZ_4K
, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 8 * 1024,
21 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 8 * 1024,
22 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
23 0, 0, BOOKE_PAGESZ_4K
, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR
+ 12 * 1024,
25 CONFIG_SYS_INIT_RAM_ADDR_PHYS
+ 12 * 1024,
26 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
27 0, 0, BOOKE_PAGESZ_4K
, 0),
30 /* *I*** - Covers boot page */
31 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
33 * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
34 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
36 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR
, CONFIG_SYS_INIT_L3_ADDR
,
37 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
38 0, 0, BOOKE_PAGESZ_256K
, 1),
40 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
41 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
42 0, 0, BOOKE_PAGESZ_4K
, 1),
46 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR
, CONFIG_SYS_CCSRBAR_PHYS
,
47 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
48 0, 1, BOOKE_PAGESZ_16M
, 1),
50 /* *I*G* - Flash, localbus */
51 /* This will be changed to *I*G* after relocation to RAM. */
52 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE
, CONFIG_SYS_FLASH_BASE_PHYS
,
53 MAS3_SX
|MAS3_SR
, MAS2_W
|MAS2_G
,
54 0, 2, BOOKE_PAGESZ_256M
, 1),
56 #ifndef CONFIG_SPL_BUILD
58 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT
, CONFIG_SYS_PCIE1_MEM_PHYS
,
59 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
60 0, 3, BOOKE_PAGESZ_1G
, 1),
63 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT
, CONFIG_SYS_PCIE1_IO_PHYS
,
64 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
65 0, 4, BOOKE_PAGESZ_256K
, 1),
68 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
69 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
, CONFIG_SYS_BMAN_MEM_PHYS
,
70 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
71 0, 5, BOOKE_PAGESZ_16M
, 1),
72 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE
+ 0x01000000,
73 CONFIG_SYS_BMAN_MEM_PHYS
+ 0x01000000,
74 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
75 0, 6, BOOKE_PAGESZ_16M
, 1),
77 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
78 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
, CONFIG_SYS_QMAN_MEM_PHYS
,
79 MAS3_SX
|MAS3_SW
|MAS3_SR
, 0,
80 0, 7, BOOKE_PAGESZ_16M
, 1),
81 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE
+ 0x01000000,
82 CONFIG_SYS_QMAN_MEM_PHYS
+ 0x01000000,
83 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
84 0, 8, BOOKE_PAGESZ_16M
, 1),
87 #ifdef CONFIG_SYS_DCSRBAR_PHYS
88 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR
, CONFIG_SYS_DCSRBAR_PHYS
,
89 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
90 0, 9, BOOKE_PAGESZ_4M
, 1),
92 #ifdef CONFIG_SYS_NAND_BASE
93 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE
, CONFIG_SYS_NAND_BASE_PHYS
,
94 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
95 0, 10, BOOKE_PAGESZ_64K
, 1),
97 #ifdef CONFIG_SYS_CPLD_BASE
98 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE
, CONFIG_SYS_CPLD_BASE_PHYS
,
99 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_I
|MAS2_G
,
100 0, 11, BOOKE_PAGESZ_256K
, 1),
103 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
104 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE
, CONFIG_SYS_DDR_SDRAM_BASE
,
105 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_M
,
106 0, 12, BOOKE_PAGESZ_1G
, 1),
107 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE
+ 0x40000000,
108 CONFIG_SYS_DDR_SDRAM_BASE
+ 0x40000000,
109 MAS3_SX
|MAS3_SW
|MAS3_SR
, MAS2_M
,
110 0, 13, BOOKE_PAGESZ_1G
, 1)
112 /* entry 14 and 15 has been used hard coded, they will be disabled
113 * in cpu_init_f, so if needed more, will use entry 16 later.
117 int num_tlb_entries
= ARRAY_SIZE(tlb_table
);