board/freescale/t1040qds/t1040qds.c

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/cache.h>
  15 #include <asm/immap_85xx.h>
  16 #include <asm/fsl_law.h>
  17 #include <asm/fsl_serdes.h>
  18 #include <asm/fsl_portals.h>
  19 #include <asm/fsl_liodn.h>
  20 #include <fm_eth.h>
  21
  22 #include "../common/qixis.h"
  23 #include "t1040qds.h"
  24 #include "t1040qds_qixis.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 int checkboard(void)
  29 {
  30         char buf[64];
  31         u8 sw;
  32         struct cpu_type *cpu = gd->arch.cpu;
  33         static const char *const freq[] = {"100", "125", "156.25", "161.13",
  34                                                 "122.88", "122.88", "122.88"};
  35         int clock;
  36
  37         printf("Board: %sQDS, ", cpu->name);
  38         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  39                QIXIS_READ(id), QIXIS_READ(arch));
  40
  41         sw = QIXIS_READ(brdcfg[0]);
  42         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  43
  44         if (sw < 0x8)
  45                 printf("vBank: %d\n", sw);
  46         else if (sw == 0x8)
  47                 puts("PromJet\n");
  48         else if (sw == 0x9)
  49                 puts("NAND\n");
  50         else if (sw == 0x15)
  51                 printf("IFCCard\n");
  52         else
  53                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  54
  55         printf("FPGA: v%d (%s), build %d",
  56                (int)QIXIS_READ(scver), qixis_read_tag(buf),
  57                (int)qixis_read_minor());
  58         /* the timestamp string contains "\n" at the end */
  59         printf(" on %s", qixis_read_time(buf));
  60
  61         /*
  62          * Display the actual SERDES reference clocks as configured by the
  63          * dip switches on the board.  Note that the SWx registers could
  64          * technically be set to force the reference clocks to match the
  65          * values that the SERDES expects (or vice versa).  For now, however,
  66          * we just display both values and hope the user notices when they
  67          * don't match.
  68          */
  69         puts("SERDES Reference: ");
  70         sw = QIXIS_READ(brdcfg[2]);
  71         clock = (sw >> 6) & 3;
  72         printf("Clock1=%sMHz ", freq[clock]);
  73         clock = (sw >> 4) & 3;
  74         printf("Clock2=%sMHz\n", freq[clock]);
  75
  76         return 0;
  77 }
  78
  79 int select_i2c_ch_pca9547(u8 ch)
  80 {
  81         int ret;
  82
  83         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  84         if (ret) {
  85                 puts("PCA: failed to select proper channel\n");
  86                 return ret;
  87         }
  88
  89         return 0;
  90 }
  91
  92 int board_early_init_r(void)
  93 {
  94 #ifdef CONFIG_SYS_FLASH_BASE
  95         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  96         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  97
  98         /*
  99          * Remap Boot flash + PROMJET region to caching-inhibited
 100          * so that flash can be erased properly.
 101          */
 102
 103         /* Flush d-cache and invalidate i-cache of any FLASH data */
 104         flush_dcache();
 105         invalidate_icache();
 106
 107         /* invalidate existing TLB entry for flash + promjet */
 108         disable_tlb(flash_esel);
 109
 110         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 111                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 112                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 113 #endif
 114         set_liodns();
 115 #ifdef CONFIG_SYS_DPAA_QBMAN
 116         setup_portals();
 117 #endif
 118         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 119
 120         return 0;
 121 }
 122
 123 unsigned long get_board_sys_clk(void)
 124 {
 125         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 126
 127         switch (sysclk_conf & 0x0F) {
 128         case QIXIS_SYSCLK_64:
 129                 return 64000000;
 130         case QIXIS_SYSCLK_83:
 131                 return 83333333;
 132         case QIXIS_SYSCLK_100:
 133                 return 100000000;
 134         case QIXIS_SYSCLK_125:
 135                 return 125000000;
 136         case QIXIS_SYSCLK_133:
 137                 return 133333333;
 138         case QIXIS_SYSCLK_150:
 139                 return 150000000;
 140         case QIXIS_SYSCLK_160:
 141                 return 160000000;
 142         case QIXIS_SYSCLK_166:
 143                 return 166666666;
 144         }
 145         return 66666666;
 146 }
 147
 148 unsigned long get_board_ddr_clk(void)
 149 {
 150         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 151
 152         switch ((ddrclk_conf & 0x30) >> 4) {
 153         case QIXIS_DDRCLK_100:
 154                 return 100000000;
 155         case QIXIS_DDRCLK_125:
 156                 return 125000000;
 157         case QIXIS_DDRCLK_133:
 158                 return 133333333;
 159         }
 160         return 66666666;
 161 }
 162
 163 static const char *serdes_clock_to_string(u32 clock)
 164 {
 165         switch (clock) {
 166         case SRDS_PLLCR0_RFCK_SEL_100:
 167                 return "100";
 168         case SRDS_PLLCR0_RFCK_SEL_125:
 169                 return "125";
 170         case SRDS_PLLCR0_RFCK_SEL_156_25:
 171                 return "156.25";
 172         default:
 173                 return "Unknown frequency";
 174         }
 175 }
 176
 177 #define NUM_SRDS_BANKS  2
 178 int misc_init_r(void)
 179 {
 180         u8 sw;
 181         serdes_corenet_t *srds_regs =
 182                 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
 183         u32 actual[NUM_SRDS_BANKS] = { 0 };
 184         int i;
 185
 186         sw = QIXIS_READ(brdcfg[2]);
 187         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 188                 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
 189                 switch (clock) {
 190                 case 0:
 191                         actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
 192                         break;
 193                 case 1:
 194                         actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
 195                         break;
 196                 case 2:
 197                         actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
 198                         break;
 199                 }
 200         }
 201
 202         puts("SerDes1");
 203         for (i = 0; i < NUM_SRDS_BANKS; i++) {
 204                 u32 pllcr0 = srds_regs->bank[i].pllcr0;
 205                 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
 206                 if (expected != actual[i]) {
 207                         printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
 208                                i + 1, serdes_clock_to_string(expected),
 209                                serdes_clock_to_string(actual[i]));
 210                 }
 211         }
 212
 213         return 0;
 214 }
 215
 216 void ft_board_setup(void *blob, bd_t *bd)
 217 {
 218         phys_addr_t base;
 219         phys_size_t size;
 220
 221         ft_cpu_setup(blob, bd);
 222
 223         base = getenv_bootm_low();
 224         size = getenv_bootm_size();
 225
 226         fdt_fixup_memory(blob, (u64)base, (u64)size);
 227
 228 #ifdef CONFIG_PCI
 229         pci_of_setup(blob, bd);
 230 #endif
 231
 232         fdt_fixup_liodn(blob);
 233
 234 #ifdef CONFIG_HAS_FSL_DR_USB
 235         fdt_fixup_dr_usb(blob, bd);
 236 #endif
 237
 238 #ifdef CONFIG_SYS_DPAA_FMAN
 239         fdt_fixup_fman_ethernet(blob);
 240 #endif
 241 }
 242
 243 void qixis_dump_switch(void)
 244 {
 245         int i, nr_of_cfgsw;
 246
 247         QIXIS_WRITE(cms[0], 0x00);
 248         nr_of_cfgsw = QIXIS_READ(cms[1]);
 249
 250         puts("DIP switch settings dump:\n");
 251         for (i = 1; i <= nr_of_cfgsw; i++) {
 252                 QIXIS_WRITE(cms[0], i);
 253                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 254         }
 255 }