board/freescale/t104xrdb/ddr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 #ifndef __DDR_H__
   7 #define __DDR_H__
   8 struct board_specific_parameters {
   9         u32 n_ranks;
  10         u32 datarate_mhz_high;
  11         u32 rank_gb;
  12         u32 clk_adjust;
  13         u32 wrlvl_start;
  14         u32 wrlvl_ctl_2;
  15         u32 wrlvl_ctl_3;
  16 };
  17
  18 /*
  19  * These tables contain all valid speeds we want to override with board
  20  * specific parameters. datarate_mhz_high values need to be in ascending order
  21  * for each n_ranks group.
  22  */
  23
  24 static const struct board_specific_parameters udimm0[] = {
  25         /*
  26          * memory controller 0
  27          *   num|  hi| rank|  clk| wrlvl |   wrlvl
  28          * ranks| mhz| GB  |adjst| start |   ctl2
  29          */
  30 #ifdef CONFIG_SYS_FSL_DDR4
  31         {2,  1600, 4, 8,     6, 0x07090A0c, 0x0e0f100a},
  32 #elif defined(CONFIG_SYS_FSL_DDR3)
  33         {2,  833,  4, 8,     6, 0x06060607, 0x08080807},
  34         {2,  833,  0, 8,     6, 0x06060607, 0x08080807},
  35         {2,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
  36         {2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
  37         {2,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
  38         {2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
  39         {1,  833,  4, 8,     6, 0x06060607, 0x08080807},
  40         {1,  833,  0, 8,     6, 0x06060607, 0x08080807},
  41         {1,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
  42         {1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
  43         {1,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
  44         {1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
  45 #else
  46 #error DDR type not defined
  47 #endif
  48         {}
  49 };
  50
  51 #endif
  52
  53 static const struct board_specific_parameters *udimms[] = {
  54         udimm0,
  55 };