2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 or later as published by the Free Software Foundation.
13 #include <fsl_ddr_sdram.h>
14 #include <fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 void fsl_ddr_board_options(memctl_options_t
*popts
,
22 unsigned int ctrl_num
)
24 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
28 printf("Not supported controller number %d\n", ctrl_num
);
35 * we use identical timing for all slots. If needed, change the code
36 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
38 if (popts
->registered_dimm_en
)
43 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
44 * freqency and n_banks specified in board_specific_parameters table.
46 ddr_freq
= get_ddr_freq(0) / 1000000;
47 while (pbsp
->datarate_mhz_high
) {
48 if (pbsp
->n_ranks
== pdimm
->n_ranks
&&
49 (pdimm
->rank_density
>> 30) >= pbsp
->rank_gb
) {
50 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
51 popts
->clk_adjust
= pbsp
->clk_adjust
;
52 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
53 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
54 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
63 printf("Error: board specific timing not found");
64 printf("for data rate %lu MT/s\n", ddr_freq
);
65 printf("Trying to use the highest speed (%u) parameters\n",
66 pbsp_highest
->datarate_mhz_high
);
67 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
68 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
69 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
70 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
72 panic("DIMM is not supported by this board");
75 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
76 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
77 "wrlvl_ctrl_3 0x%x\n",
78 pbsp
->n_ranks
, pbsp
->datarate_mhz_high
, pbsp
->rank_gb
,
79 pbsp
->clk_adjust
, pbsp
->wrlvl_start
, pbsp
->wrlvl_ctl_2
,
83 * Factors to consider for half-strength driver enable:
84 * - number of DIMMs installed
86 popts
->half_strength_driver_enable
= 0;
88 * Write leveling override
90 popts
->wrlvl_override
= 1;
91 popts
->wrlvl_sample
= 0xf;
94 * Rtt and Rtt_WR override
96 popts
->rtt_override
= 0;
98 /* Enable ZQ calibration */
101 /* DHC_EN =1, ODT = 75 Ohm */
102 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm
);
103 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_75ohm
);
106 phys_size_t
initdram(int board_type
)
108 phys_size_t dram_size
;
110 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
111 puts("Initializing....using SPD\n");
112 dram_size
= fsl_ddr_sdram();
114 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
115 dram_size
*= 0x100000;
117 /* DDR has been initialised by first stage boot loader */
118 dram_size
= fsl_ddr_sdram_size();