2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 or later as published by the Free Software Foundation.
13 #include <fsl_ddr_sdram.h>
14 #include <fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 void fsl_ddr_board_options(memctl_options_t
*popts
,
22 unsigned int ctrl_num
)
24 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
28 printf("Not supported controller number %d\n", ctrl_num
);
36 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
37 * freqency and n_banks specified in board_specific_parameters table.
39 ddr_freq
= get_ddr_freq(0) / 1000000;
40 while (pbsp
->datarate_mhz_high
) {
41 if (pbsp
->n_ranks
== pdimm
->n_ranks
&&
42 (pdimm
->rank_density
>> 30) >= pbsp
->rank_gb
) {
43 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
44 popts
->clk_adjust
= pbsp
->clk_adjust
;
45 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
46 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
47 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
56 printf("Error: board specific timing not found");
57 printf("for data rate %lu MT/s\n", ddr_freq
);
58 printf("Trying to use the highest speed (%u) parameters\n",
59 pbsp_highest
->datarate_mhz_high
);
60 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
61 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
62 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
63 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
65 panic("DIMM is not supported by this board");
68 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
69 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
70 "wrlvl_ctrl_3 0x%x\n",
71 pbsp
->n_ranks
, pbsp
->datarate_mhz_high
, pbsp
->rank_gb
,
72 pbsp
->clk_adjust
, pbsp
->wrlvl_start
, pbsp
->wrlvl_ctl_2
,
76 * Factors to consider for half-strength driver enable:
77 * - number of DIMMs installed
79 popts
->half_strength_driver_enable
= 0;
81 * Write leveling override
83 popts
->wrlvl_override
= 1;
84 popts
->wrlvl_sample
= 0xf;
87 * Rtt and Rtt_WR override
89 popts
->rtt_override
= 0;
91 /* Enable ZQ calibration */
94 /* DHC_EN =1, ODT = 75 Ohm */
95 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm
);
96 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_75ohm
);
99 phys_size_t
initdram(int board_type
)
101 phys_size_t dram_size
;
103 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
104 puts("Initializing....using SPD\n");
105 dram_size
= fsl_ddr_sdram();
107 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
108 dram_size
*= 0x100000;
110 /* DDR has been initialised by first stage boot loader */
111 dram_size
= fsl_ddr_sdram_size();