2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 or later as published by the Free Software Foundation.
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
17 DECLARE_GLOBAL_DATA_PTR
;
19 struct board_specific_parameters
{
21 u32 datarate_mhz_high
;
33 * This table contains all valid speeds we want to override with board
34 * specific parameters. datarate_mhz_high values need to be in ascending order
35 * for each n_ranks group.
37 static const struct board_specific_parameters udimm0
[] = {
40 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
41 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
43 {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
44 {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
45 {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
46 {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
47 {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
48 {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
49 {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
50 {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
51 {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
52 {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
57 * The three slots have slightly different timing. The center values are good
58 * for all slots. We use identical speed tables for them. In future use, if
59 * DIMMs require separated tables, make more entries as needed.
61 static const struct board_specific_parameters
*udimms
[] = {
65 static const struct board_specific_parameters rdimm0
[] = {
68 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
69 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
71 {4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
72 {4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
73 {4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
74 {2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
75 {2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
76 {2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
77 {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
78 {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
79 {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
80 {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
85 * The three slots have slightly different timing. See comments above.
87 static const struct board_specific_parameters
*rdimms
[] = {
91 void fsl_ddr_board_options(memctl_options_t
*popts
,
93 unsigned int ctrl_num
)
95 const struct board_specific_parameters
*pbsp
, *pbsp_highest
= NULL
;
99 printf("Not supported controller number %d\n", ctrl_num
);
106 * we use identical timing for all slots. If needed, change the code
107 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
109 if (popts
->registered_dimm_en
)
115 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
116 * freqency and n_banks specified in board_specific_parameters table.
118 ddr_freq
= get_ddr_freq(0) / 1000000;
119 while (pbsp
->datarate_mhz_high
) {
120 if (pbsp
->n_ranks
== pdimm
->n_ranks
&&
121 (pdimm
->rank_density
>> 30) >= pbsp
->rank_gb
) {
122 if (ddr_freq
<= pbsp
->datarate_mhz_high
) {
123 popts
->cpo_override
= pbsp
->cpo
;
124 popts
->write_data_delay
=
125 pbsp
->write_data_delay
;
126 popts
->clk_adjust
= pbsp
->clk_adjust
;
127 popts
->wrlvl_start
= pbsp
->wrlvl_start
;
128 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
129 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
130 popts
->twoT_en
= pbsp
->force_2T
;
139 printf("Error: board specific timing not found "
140 "for data rate %lu MT/s\n"
141 "Trying to use the highest speed (%u) parameters\n",
142 ddr_freq
, pbsp_highest
->datarate_mhz_high
);
143 popts
->cpo_override
= pbsp_highest
->cpo
;
144 popts
->write_data_delay
= pbsp_highest
->write_data_delay
;
145 popts
->clk_adjust
= pbsp_highest
->clk_adjust
;
146 popts
->wrlvl_start
= pbsp_highest
->wrlvl_start
;
147 popts
->wrlvl_ctl_2
= pbsp
->wrlvl_ctl_2
;
148 popts
->wrlvl_ctl_3
= pbsp
->wrlvl_ctl_3
;
149 popts
->twoT_en
= pbsp_highest
->force_2T
;
151 panic("DIMM is not supported by this board");
154 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
155 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
156 "wrlvl_ctrl_3 0x%x\n",
157 pbsp
->n_ranks
, pbsp
->datarate_mhz_high
, pbsp
->rank_gb
,
158 pbsp
->clk_adjust
, pbsp
->wrlvl_start
, pbsp
->wrlvl_ctl_2
,
162 * Factors to consider for half-strength driver enable:
163 * - number of DIMMs installed
165 popts
->half_strength_driver_enable
= 0;
167 * Write leveling override
169 popts
->wrlvl_override
= 1;
170 popts
->wrlvl_sample
= 0xf;
173 * Rtt and Rtt_WR override
175 popts
->rtt_override
= 0;
177 /* Enable ZQ calibration */
180 /* DHC_EN =1, ODT = 75 Ohm */
181 popts
->ddr_cdr1
= DDR_CDR1_DHC_EN
| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm
);
182 popts
->ddr_cdr2
= DDR_CDR2_ODT(DDR_CDR_ODT_75ohm
);
185 phys_size_t
initdram(int board_type
)
187 phys_size_t dram_size
;
189 puts("Initializing....using SPD\n");
191 dram_size
= fsl_ddr_sdram();
193 dram_size
= setup_ddr_tlbs(dram_size
/ 0x100000);
194 dram_size
*= 0x100000;