1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012 Freescale Semiconductor, Inc.
11 #include <asm/processor.h>
12 #include <asm/cache.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_law.h>
15 #include <fsl_ddr_sdram.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
24 #include <fsl_dtsec.h>
25 #include <asm/fsl_serdes.h>
27 #include "../common/qixis.h"
28 #include "../common/fman.h"
30 #include "t4240qds_qixis.h"
32 #define EMI_NONE 0xFFFFFFFF
41 /* Slot6 and Slot8 do not have EMI connections */
43 static int mdio_mux
[NUM_FM_PORTS
];
45 static const char *mdio_names
[] = {
57 static u8 lane_to_slot_fsm1
[] = {1, 1, 1, 1, 2, 2, 2, 2};
58 static u8 lane_to_slot_fsm2
[] = {3, 3, 3, 3, 4, 4, 4, 4};
59 static u8 slot_qsgmii_phyaddr
[5][4] = {
60 {0, 0, 0, 0},/* not used, to make index match slot No. */
66 static u8 qsgmiiphy_fix
[NUM_FM_PORTS
] = {0};
68 static const char *t4240qds_mdio_name_for_muxval(u8 muxval
)
70 return mdio_names
[muxval
];
73 struct mii_dev
*mii_dev_for_muxval(u8 muxval
)
76 const char *name
= t4240qds_mdio_name_for_muxval(muxval
);
79 printf("No bus for muxval %x\n", muxval
);
83 bus
= miiphy_get_dev_by_name(name
);
86 printf("No bus by name %s\n", name
);
93 struct t4240qds_mdio
{
95 struct mii_dev
*realbus
;
98 static void t4240qds_mux_mdio(u8 muxval
)
101 if ((muxval
< 6) || (muxval
== 7)) {
102 brdcfg4
= QIXIS_READ(brdcfg
[4]);
103 brdcfg4
&= ~BRDCFG4_EMISEL_MASK
;
104 brdcfg4
|= (muxval
<< BRDCFG4_EMISEL_SHIFT
);
105 QIXIS_WRITE(brdcfg
[4], brdcfg4
);
109 static int t4240qds_mdio_read(struct mii_dev
*bus
, int addr
, int devad
,
112 struct t4240qds_mdio
*priv
= bus
->priv
;
114 t4240qds_mux_mdio(priv
->muxval
);
116 return priv
->realbus
->read(priv
->realbus
, addr
, devad
, regnum
);
119 static int t4240qds_mdio_write(struct mii_dev
*bus
, int addr
, int devad
,
120 int regnum
, u16 value
)
122 struct t4240qds_mdio
*priv
= bus
->priv
;
124 t4240qds_mux_mdio(priv
->muxval
);
126 return priv
->realbus
->write(priv
->realbus
, addr
, devad
, regnum
, value
);
129 static int t4240qds_mdio_reset(struct mii_dev
*bus
)
131 struct t4240qds_mdio
*priv
= bus
->priv
;
133 return priv
->realbus
->reset(priv
->realbus
);
136 static int t4240qds_mdio_init(char *realbusname
, u8 muxval
)
138 struct t4240qds_mdio
*pmdio
;
139 struct mii_dev
*bus
= mdio_alloc();
142 printf("Failed to allocate T4240QDS MDIO bus\n");
146 pmdio
= malloc(sizeof(*pmdio
));
148 printf("Failed to allocate T4240QDS private data\n");
153 bus
->read
= t4240qds_mdio_read
;
154 bus
->write
= t4240qds_mdio_write
;
155 bus
->reset
= t4240qds_mdio_reset
;
156 strcpy(bus
->name
, t4240qds_mdio_name_for_muxval(muxval
));
158 pmdio
->realbus
= miiphy_get_dev_by_name(realbusname
);
160 if (!pmdio
->realbus
) {
161 printf("No bus with name %s\n", realbusname
);
167 pmdio
->muxval
= muxval
;
170 return mdio_register(bus
);
173 void board_ft_fman_fixup_port(void *blob
, char * prop
, phys_addr_t pa
,
174 enum fm_port port
, int offset
)
176 int interface
= fm_info_get_enet_if(port
);
177 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
178 u32 prtcl2
= in_be32(&gur
->rcwsr
[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL
;
180 prtcl2
>>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT
;
182 if (interface
== PHY_INTERFACE_MODE_SGMII
||
183 interface
== PHY_INTERFACE_MODE_QSGMII
) {
186 if (qsgmiiphy_fix
[port
])
187 fdt_set_phy_handle(blob
, prop
, pa
,
191 if (qsgmiiphy_fix
[port
])
192 fdt_set_phy_handle(blob
, prop
, pa
,
196 if (qsgmiiphy_fix
[port
])
197 fdt_set_phy_handle(blob
, prop
, pa
,
201 if (qsgmiiphy_fix
[port
])
202 fdt_set_phy_handle(blob
, prop
, pa
,
206 if (qsgmiiphy_fix
[port
])
207 fdt_set_phy_handle(blob
, prop
, pa
,
211 if (qsgmiiphy_fix
[port
])
212 fdt_set_phy_handle(blob
, prop
, pa
,
215 fdt_set_phy_handle(blob
, prop
, pa
,
219 if (qsgmiiphy_fix
[port
])
220 fdt_set_phy_handle(blob
, prop
, pa
,
223 fdt_set_phy_handle(blob
, prop
, pa
,
227 if (qsgmiiphy_fix
[port
])
228 fdt_set_phy_handle(blob
, prop
, pa
,
232 if (qsgmiiphy_fix
[port
])
233 fdt_set_phy_handle(blob
, prop
, pa
,
237 if (qsgmiiphy_fix
[port
])
238 fdt_set_phy_handle(blob
, prop
, pa
,
242 if (qsgmiiphy_fix
[port
])
243 fdt_set_phy_handle(blob
, prop
, pa
,
247 if (qsgmiiphy_fix
[port
])
248 fdt_set_phy_handle(blob
, prop
, pa
,
252 if (qsgmiiphy_fix
[port
])
253 fdt_set_phy_handle(blob
, prop
, pa
,
256 fdt_set_phy_handle(blob
, prop
, pa
,
260 if (qsgmiiphy_fix
[port
])
261 fdt_set_phy_handle(blob
, prop
, pa
,
264 fdt_set_phy_handle(blob
, prop
, pa
,
270 } else if (interface
== PHY_INTERFACE_MODE_XGMII
&&
271 ((prtcl2
== 55) || (prtcl2
== 57))) {
273 * if the 10G is XFI, check hwconfig to see what is the
274 * media type, there are two types, fiber or copper,
275 * fix the dtb accordingly.
278 struct fixed_link f_link
;
279 char lane_mode
[20] = {"10GBASE-KR"};
280 char buf
[32] = "serdes-2,";
285 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
287 fdt_set_phy_handle(blob
, prop
, pa
,
289 sprintf(buf
, "%s%s%s", buf
, "lane-a,",
294 if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
296 fdt_set_phy_handle(blob
, prop
, pa
,
298 sprintf(buf
, "%s%s%s", buf
, "lane-b,",
303 if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) {
305 fdt_set_phy_handle(blob
, prop
, pa
,
307 sprintf(buf
, "%s%s%s", buf
, "lane-d,",
312 if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) {
314 fdt_set_phy_handle(blob
, prop
, pa
,
316 sprintf(buf
, "%s%s%s", buf
, "lane-c,",
325 /* fixed-link is used for XFI fiber cable */
326 fdt_delprop(blob
, offset
, "phy-handle");
327 f_link
.phy_id
= port
;
329 f_link
.link_speed
= 10000;
331 f_link
.asym_pause
= 0;
332 fdt_setprop(blob
, offset
, "fixed-link", &f_link
,
335 /* set property for copper cable */
336 off
= fdt_node_offset_by_compat_reg(blob
,
337 "fsl,fman-memac-mdio", pa
+ 0x1000);
338 fdt_setprop_string(blob
, off
, "lane-instance", buf
);
343 void fdt_fixup_board_enet(void *fdt
)
346 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
347 u32 prtcl2
= in_be32(&gur
->rcwsr
[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL
;
349 prtcl2
>>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT
;
350 for (i
= FM1_DTSEC1
; i
< NUM_FM_PORTS
; i
++) {
351 switch (fm_info_get_enet_if(i
)) {
352 case PHY_INTERFACE_MODE_SGMII
:
353 case PHY_INTERFACE_MODE_QSGMII
:
354 switch (mdio_mux
[i
]) {
356 fdt_status_okay_by_alias(fdt
, "emi1_slot1");
359 fdt_status_okay_by_alias(fdt
, "emi1_slot2");
362 fdt_status_okay_by_alias(fdt
, "emi1_slot3");
365 fdt_status_okay_by_alias(fdt
, "emi1_slot4");
371 case PHY_INTERFACE_MODE_XGMII
:
372 /* check if it's XFI interface for 10g */
373 if ((prtcl2
== 55) || (prtcl2
== 57)) {
374 if (i
== FM1_10GEC1
&& hwconfig_sub(
375 "fsl_10gkr_copper", "fm1_10g1"))
376 fdt_status_okay_by_alias(
377 fdt
, "xfi_pcs_mdio1");
378 if (i
== FM1_10GEC2
&& hwconfig_sub(
379 "fsl_10gkr_copper", "fm1_10g2"))
380 fdt_status_okay_by_alias(
381 fdt
, "xfi_pcs_mdio2");
382 if (i
== FM2_10GEC1
&& hwconfig_sub(
383 "fsl_10gkr_copper", "fm2_10g1"))
384 fdt_status_okay_by_alias(
385 fdt
, "xfi_pcs_mdio3");
386 if (i
== FM2_10GEC2
&& hwconfig_sub(
387 "fsl_10gkr_copper", "fm2_10g2"))
388 fdt_status_okay_by_alias(
389 fdt
, "xfi_pcs_mdio4");
394 fdt_status_okay_by_alias(fdt
, "emi2_xauislot1");
397 fdt_status_okay_by_alias(fdt
, "emi2_xauislot2");
400 fdt_status_okay_by_alias(fdt
, "emi2_xauislot3");
403 fdt_status_okay_by_alias(fdt
, "emi2_xauislot4");
415 static void initialize_qsgmiiphy_fix(void)
420 for (i
= 1; i
<= 4; i
++) {
422 * Try to read if a SGMII card is used, we do it slot by slot.
423 * if a SGMII PHY address is valid on a slot, then we mark
424 * all ports on the slot, then fix the PHY address for the
425 * marked port when doing dtb fixup.
427 if (miiphy_read(mdio_names
[i
],
428 SGMII_CARD_PORT1_PHY_ADDR
, MII_PHYSID2
, ®
) != 0) {
429 debug("Slot%d PHY ID register 2 read failed\n", i
);
433 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i
, reg
);
436 /* No physical device present at this address */
442 qsgmiiphy_fix
[FM1_DTSEC5
] = 1;
443 qsgmiiphy_fix
[FM1_DTSEC6
] = 1;
444 qsgmiiphy_fix
[FM1_DTSEC9
] = 1;
445 qsgmiiphy_fix
[FM1_DTSEC10
] = 1;
446 slot_qsgmii_phyaddr
[1][0] = SGMII_CARD_PORT1_PHY_ADDR
;
447 slot_qsgmii_phyaddr
[1][1] = SGMII_CARD_PORT2_PHY_ADDR
;
448 slot_qsgmii_phyaddr
[1][2] = SGMII_CARD_PORT3_PHY_ADDR
;
449 slot_qsgmii_phyaddr
[1][3] = SGMII_CARD_PORT4_PHY_ADDR
;
452 qsgmiiphy_fix
[FM1_DTSEC1
] = 1;
453 qsgmiiphy_fix
[FM1_DTSEC2
] = 1;
454 qsgmiiphy_fix
[FM1_DTSEC3
] = 1;
455 qsgmiiphy_fix
[FM1_DTSEC4
] = 1;
456 slot_qsgmii_phyaddr
[2][0] = SGMII_CARD_PORT1_PHY_ADDR
;
457 slot_qsgmii_phyaddr
[2][1] = SGMII_CARD_PORT2_PHY_ADDR
;
458 slot_qsgmii_phyaddr
[2][2] = SGMII_CARD_PORT3_PHY_ADDR
;
459 slot_qsgmii_phyaddr
[2][3] = SGMII_CARD_PORT4_PHY_ADDR
;
462 qsgmiiphy_fix
[FM2_DTSEC5
] = 1;
463 qsgmiiphy_fix
[FM2_DTSEC6
] = 1;
464 qsgmiiphy_fix
[FM2_DTSEC9
] = 1;
465 qsgmiiphy_fix
[FM2_DTSEC10
] = 1;
466 slot_qsgmii_phyaddr
[3][0] = SGMII_CARD_PORT1_PHY_ADDR
;
467 slot_qsgmii_phyaddr
[3][1] = SGMII_CARD_PORT2_PHY_ADDR
;
468 slot_qsgmii_phyaddr
[3][2] = SGMII_CARD_PORT3_PHY_ADDR
;
469 slot_qsgmii_phyaddr
[3][3] = SGMII_CARD_PORT4_PHY_ADDR
;
472 qsgmiiphy_fix
[FM2_DTSEC1
] = 1;
473 qsgmiiphy_fix
[FM2_DTSEC2
] = 1;
474 qsgmiiphy_fix
[FM2_DTSEC3
] = 1;
475 qsgmiiphy_fix
[FM2_DTSEC4
] = 1;
476 slot_qsgmii_phyaddr
[4][0] = SGMII_CARD_PORT1_PHY_ADDR
;
477 slot_qsgmii_phyaddr
[4][1] = SGMII_CARD_PORT2_PHY_ADDR
;
478 slot_qsgmii_phyaddr
[4][2] = SGMII_CARD_PORT3_PHY_ADDR
;
479 slot_qsgmii_phyaddr
[4][3] = SGMII_CARD_PORT4_PHY_ADDR
;
487 int board_eth_init(bd_t
*bis
)
489 #if defined(CONFIG_FMAN_ENET)
490 int i
, idx
, lane
, slot
, interface
;
491 struct memac_mdio_info dtsec_mdio_info
;
492 struct memac_mdio_info tgec_mdio_info
;
493 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
494 u32 srds_prtcl_s1
, srds_prtcl_s2
;
496 srds_prtcl_s1
= in_be32(&gur
->rcwsr
[4]) &
497 FSL_CORENET2_RCWSR4_SRDS1_PRTCL
;
498 srds_prtcl_s1
>>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT
;
499 srds_prtcl_s2
= in_be32(&gur
->rcwsr
[4]) &
500 FSL_CORENET2_RCWSR4_SRDS2_PRTCL
;
501 srds_prtcl_s2
>>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT
;
503 /* Initialize the mdio_mux array so we can recognize empty elements */
504 for (i
= 0; i
< NUM_FM_PORTS
; i
++)
505 mdio_mux
[i
] = EMI_NONE
;
507 dtsec_mdio_info
.regs
=
508 (struct memac_mdio_controller
*)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR
;
510 dtsec_mdio_info
.name
= DEFAULT_FM_MDIO_NAME
;
512 /* Register the 1G MDIO bus */
513 fm_memac_mdio_init(bis
, &dtsec_mdio_info
);
515 tgec_mdio_info
.regs
=
516 (struct memac_mdio_controller
*)CONFIG_SYS_FM2_TGEC_MDIO_ADDR
;
517 tgec_mdio_info
.name
= DEFAULT_FM_TGEC_MDIO_NAME
;
519 /* Register the 10G MDIO bus */
520 fm_memac_mdio_init(bis
, &tgec_mdio_info
);
522 /* Register the muxing front-ends to the MDIO buses */
523 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_RGMII
);
524 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT1
);
525 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT2
);
526 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT3
);
527 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT4
);
528 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT5
);
529 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME
, EMI1_SLOT7
);
530 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME
, EMI2
);
532 initialize_qsgmiiphy_fix();
534 switch (srds_prtcl_s1
) {
538 /* XAUI/HiGig in Slot1 and Slot2 */
539 fm_info_set_phy_address(FM1_10GEC1
, FM1_10GEC1_PHY_ADDR
);
540 fm_info_set_phy_address(FM1_10GEC2
, FM1_10GEC2_PHY_ADDR
);
546 /* SGMII in Slot1 and Slot2 */
547 fm_info_set_phy_address(FM1_DTSEC1
, slot_qsgmii_phyaddr
[2][0]);
548 fm_info_set_phy_address(FM1_DTSEC2
, slot_qsgmii_phyaddr
[2][1]);
549 fm_info_set_phy_address(FM1_DTSEC3
, slot_qsgmii_phyaddr
[2][2]);
550 fm_info_set_phy_address(FM1_DTSEC4
, slot_qsgmii_phyaddr
[2][3]);
551 fm_info_set_phy_address(FM1_DTSEC5
, slot_qsgmii_phyaddr
[1][0]);
552 fm_info_set_phy_address(FM1_DTSEC6
, slot_qsgmii_phyaddr
[1][1]);
553 if ((srds_prtcl_s2
!= 55) && (srds_prtcl_s2
!= 57)) {
554 fm_info_set_phy_address(FM1_DTSEC9
,
555 slot_qsgmii_phyaddr
[1][3]);
556 fm_info_set_phy_address(FM1_DTSEC10
,
557 slot_qsgmii_phyaddr
[1][2]);
562 fm_info_set_phy_address(FM1_DTSEC1
, slot_qsgmii_phyaddr
[2][0]);
563 fm_info_set_phy_address(FM1_DTSEC2
, slot_qsgmii_phyaddr
[2][1]);
564 fm_info_set_phy_address(FM1_DTSEC3
, slot_qsgmii_phyaddr
[2][2]);
565 fm_info_set_phy_address(FM1_DTSEC4
, slot_qsgmii_phyaddr
[2][3]);
566 fm_info_set_phy_address(FM1_DTSEC5
, slot_qsgmii_phyaddr
[1][0]);
567 fm_info_set_phy_address(FM1_DTSEC6
, slot_qsgmii_phyaddr
[1][1]);
568 if ((srds_prtcl_s2
!= 55) && (srds_prtcl_s2
!= 57)) {
569 fm_info_set_phy_address(FM1_DTSEC9
,
570 slot_qsgmii_phyaddr
[1][2]);
571 fm_info_set_phy_address(FM1_DTSEC10
,
572 slot_qsgmii_phyaddr
[1][3]);
581 fm_info_set_phy_address(FM1_DTSEC5
, slot_qsgmii_phyaddr
[1][0]);
582 fm_info_set_phy_address(FM1_DTSEC6
, slot_qsgmii_phyaddr
[1][1]);
583 if ((srds_prtcl_s2
!= 55) && (srds_prtcl_s2
!= 57)) {
584 fm_info_set_phy_address(FM1_DTSEC10
,
585 slot_qsgmii_phyaddr
[1][2]);
586 fm_info_set_phy_address(FM1_DTSEC9
,
587 slot_qsgmii_phyaddr
[1][3]);
589 fm_info_set_phy_address(FM1_DTSEC1
, slot_qsgmii_phyaddr
[2][0]);
590 fm_info_set_phy_address(FM1_DTSEC2
, slot_qsgmii_phyaddr
[2][1]);
591 fm_info_set_phy_address(FM1_DTSEC3
, slot_qsgmii_phyaddr
[2][2]);
592 fm_info_set_phy_address(FM1_DTSEC4
, slot_qsgmii_phyaddr
[2][3]);
595 puts("Invalid SerDes1 protocol for T4240QDS\n");
599 for (i
= FM1_DTSEC1
; i
< FM1_DTSEC1
+ CONFIG_SYS_NUM_FM1_DTSEC
; i
++) {
600 idx
= i
- FM1_DTSEC1
;
601 interface
= fm_info_get_enet_if(i
);
603 case PHY_INTERFACE_MODE_SGMII
:
604 case PHY_INTERFACE_MODE_QSGMII
:
605 if (interface
== PHY_INTERFACE_MODE_QSGMII
) {
607 lane
= serdes_get_first_lane(FSL_SRDS_1
,
610 lane
= serdes_get_first_lane(FSL_SRDS_1
,
614 slot
= lane_to_slot_fsm1
[lane
];
615 debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
618 lane
= serdes_get_first_lane(FSL_SRDS_1
,
619 SGMII_FM1_DTSEC1
+ idx
);
622 slot
= lane_to_slot_fsm1
[lane
];
623 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
626 if (QIXIS_READ(present2
) & (1 << (slot
- 1)))
630 mdio_mux
[i
] = EMI1_SLOT1
;
632 mii_dev_for_muxval(mdio_mux
[i
]));
635 mdio_mux
[i
] = EMI1_SLOT2
;
637 mii_dev_for_muxval(mdio_mux
[i
]));
641 case PHY_INTERFACE_MODE_RGMII
:
642 /* FM1 DTSEC5 routes to RGMII with EC2 */
643 debug("FM1@DTSEC%u is RGMII at address %u\n",
646 fm_info_set_phy_address(i
, 2);
647 mdio_mux
[i
] = EMI1_RGMII
;
649 mii_dev_for_muxval(mdio_mux
[i
]));
656 for (i
= FM1_10GEC1
; i
< FM1_10GEC1
+ CONFIG_SYS_NUM_FM1_10GEC
; i
++) {
657 idx
= i
- FM1_10GEC1
;
658 switch (fm_info_get_enet_if(i
)) {
659 case PHY_INTERFACE_MODE_XGMII
:
660 if ((srds_prtcl_s2
== 55) || (srds_prtcl_s2
== 57)) {
661 /* A fake PHY address to make U-Boot happy */
662 fm_info_set_phy_address(i
, i
);
664 lane
= serdes_get_first_lane(FSL_SRDS_1
,
665 XAUI_FM1_MAC9
+ idx
);
668 slot
= lane_to_slot_fsm1
[lane
];
669 if (QIXIS_READ(present2
) & (1 << (slot
- 1)))
673 fm_info_set_mdio(i
, mii_dev_for_muxval(mdio_mux
[i
]));
680 #if (CONFIG_SYS_NUM_FMAN == 2)
681 switch (srds_prtcl_s2
) {
685 /* XAUI/HiGig in Slot3 and Slot4 */
686 fm_info_set_phy_address(FM2_10GEC1
, FM2_10GEC1_PHY_ADDR
);
687 fm_info_set_phy_address(FM2_10GEC2
, FM2_10GEC2_PHY_ADDR
);
702 /* XAUI/HiGig in Slot3, SGMII in Slot4 */
703 fm_info_set_phy_address(FM2_10GEC1
, FM2_10GEC1_PHY_ADDR
);
704 fm_info_set_phy_address(FM2_DTSEC1
, slot_qsgmii_phyaddr
[4][0]);
705 fm_info_set_phy_address(FM2_DTSEC2
, slot_qsgmii_phyaddr
[4][1]);
706 fm_info_set_phy_address(FM2_DTSEC3
, slot_qsgmii_phyaddr
[4][2]);
707 fm_info_set_phy_address(FM2_DTSEC4
, slot_qsgmii_phyaddr
[4][3]);
713 /* SGMII in Slot3 and Slot4 */
714 fm_info_set_phy_address(FM2_DTSEC1
, slot_qsgmii_phyaddr
[4][0]);
715 fm_info_set_phy_address(FM2_DTSEC2
, slot_qsgmii_phyaddr
[4][1]);
716 fm_info_set_phy_address(FM2_DTSEC3
, slot_qsgmii_phyaddr
[4][2]);
717 fm_info_set_phy_address(FM2_DTSEC4
, slot_qsgmii_phyaddr
[4][3]);
718 fm_info_set_phy_address(FM2_DTSEC5
, slot_qsgmii_phyaddr
[3][0]);
719 fm_info_set_phy_address(FM2_DTSEC6
, slot_qsgmii_phyaddr
[3][1]);
720 fm_info_set_phy_address(FM2_DTSEC9
, slot_qsgmii_phyaddr
[3][3]);
721 fm_info_set_phy_address(FM2_DTSEC10
, slot_qsgmii_phyaddr
[3][2]);
725 /* QSGMII in Slot3 and Slot4 */
726 fm_info_set_phy_address(FM2_DTSEC1
, slot_qsgmii_phyaddr
[4][0]);
727 fm_info_set_phy_address(FM2_DTSEC2
, slot_qsgmii_phyaddr
[4][1]);
728 fm_info_set_phy_address(FM2_DTSEC3
, slot_qsgmii_phyaddr
[4][2]);
729 fm_info_set_phy_address(FM2_DTSEC4
, slot_qsgmii_phyaddr
[4][3]);
730 fm_info_set_phy_address(FM2_DTSEC5
, slot_qsgmii_phyaddr
[3][0]);
731 fm_info_set_phy_address(FM2_DTSEC6
, slot_qsgmii_phyaddr
[3][1]);
732 fm_info_set_phy_address(FM2_DTSEC9
, slot_qsgmii_phyaddr
[3][2]);
733 fm_info_set_phy_address(FM2_DTSEC10
, slot_qsgmii_phyaddr
[3][3]);
742 fm_info_set_phy_address(FM2_DTSEC5
, slot_qsgmii_phyaddr
[3][0]);
743 fm_info_set_phy_address(FM2_DTSEC6
, slot_qsgmii_phyaddr
[3][1]);
744 fm_info_set_phy_address(FM2_DTSEC9
, slot_qsgmii_phyaddr
[3][3]);
745 fm_info_set_phy_address(FM2_DTSEC10
, slot_qsgmii_phyaddr
[3][2]);
746 /* QSGMII in Slot4 */
747 fm_info_set_phy_address(FM2_DTSEC1
, slot_qsgmii_phyaddr
[4][0]);
748 fm_info_set_phy_address(FM2_DTSEC2
, slot_qsgmii_phyaddr
[4][1]);
749 fm_info_set_phy_address(FM2_DTSEC3
, slot_qsgmii_phyaddr
[4][2]);
750 fm_info_set_phy_address(FM2_DTSEC4
, slot_qsgmii_phyaddr
[4][3]);
758 fm_info_set_phy_address(FM2_10GEC1
, FM2_10GEC1_PHY_ADDR
);
759 fm_info_set_phy_address(FM2_DTSEC1
, slot_qsgmii_phyaddr
[4][0]);
760 fm_info_set_phy_address(FM2_DTSEC2
, slot_qsgmii_phyaddr
[4][1]);
761 fm_info_set_phy_address(FM2_DTSEC3
, slot_qsgmii_phyaddr
[4][2]);
762 fm_info_set_phy_address(FM2_DTSEC4
, slot_qsgmii_phyaddr
[4][3]);
766 /* XFI in Slot3, SGMII in Slot4 */
767 fm_info_set_phy_address(FM2_DTSEC1
, slot_qsgmii_phyaddr
[4][0]);
768 fm_info_set_phy_address(FM2_DTSEC2
, slot_qsgmii_phyaddr
[4][1]);
769 fm_info_set_phy_address(FM2_DTSEC3
, slot_qsgmii_phyaddr
[4][2]);
770 fm_info_set_phy_address(FM2_DTSEC4
, slot_qsgmii_phyaddr
[4][3]);
773 puts("Invalid SerDes2 protocol for T4240QDS\n");
777 for (i
= FM2_DTSEC1
; i
< FM2_DTSEC1
+ CONFIG_SYS_NUM_FM2_DTSEC
; i
++) {
778 idx
= i
- FM2_DTSEC1
;
779 interface
= fm_info_get_enet_if(i
);
781 case PHY_INTERFACE_MODE_SGMII
:
782 case PHY_INTERFACE_MODE_QSGMII
:
783 if (interface
== PHY_INTERFACE_MODE_QSGMII
) {
785 lane
= serdes_get_first_lane(FSL_SRDS_2
,
788 lane
= serdes_get_first_lane(FSL_SRDS_2
,
792 slot
= lane_to_slot_fsm2
[lane
];
793 debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
796 lane
= serdes_get_first_lane(FSL_SRDS_2
,
797 SGMII_FM2_DTSEC1
+ idx
);
800 slot
= lane_to_slot_fsm2
[lane
];
801 debug("FM2@DTSEC%u expects SGMII in slot %u\n",
804 if (QIXIS_READ(present2
) & (1 << (slot
- 1)))
808 mdio_mux
[i
] = EMI1_SLOT3
;
810 mii_dev_for_muxval(mdio_mux
[i
]));
813 mdio_mux
[i
] = EMI1_SLOT4
;
815 mii_dev_for_muxval(mdio_mux
[i
]));
819 case PHY_INTERFACE_MODE_RGMII
:
821 * If DTSEC5 is RGMII, then it's routed via via EC1 to
822 * the first on-board RGMII port. If DTSEC6 is RGMII,
823 * then it's routed via via EC2 to the second on-board
826 debug("FM2@DTSEC%u is RGMII at address %u\n",
827 idx
+ 1, i
== FM2_DTSEC5
? 1 : 2);
828 fm_info_set_phy_address(i
, i
== FM2_DTSEC5
? 1 : 2);
829 mdio_mux
[i
] = EMI1_RGMII
;
830 fm_info_set_mdio(i
, mii_dev_for_muxval(mdio_mux
[i
]));
837 for (i
= FM2_10GEC1
; i
< FM2_10GEC1
+ CONFIG_SYS_NUM_FM2_10GEC
; i
++) {
838 idx
= i
- FM2_10GEC1
;
839 switch (fm_info_get_enet_if(i
)) {
840 case PHY_INTERFACE_MODE_XGMII
:
841 if ((srds_prtcl_s2
== 55) || (srds_prtcl_s2
== 57)) {
842 /* A fake PHY address to make U-Boot happy */
843 fm_info_set_phy_address(i
, i
);
845 lane
= serdes_get_first_lane(FSL_SRDS_2
,
846 XAUI_FM2_MAC9
+ idx
);
849 slot
= lane_to_slot_fsm2
[lane
];
850 if (QIXIS_READ(present2
) & (1 << (slot
- 1)))
854 fm_info_set_mdio(i
, mii_dev_for_muxval(mdio_mux
[i
]));
860 #endif /* CONFIG_SYS_NUM_FMAN */
863 #endif /* CONFIG_FMAN_ENET */
865 return pci_eth_init(bis
);