board/friendlyarm/mini2440/mini2440.c

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * (C) Copyright 2002
   7  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
   8  *
   9  * (C) Copyright 2009
  10  * Michel Pollet <buserror@gmail.com>
  11  *
  12  * (C) Copyright 2012
  13  * Gabriel Huau <contact@huau-gabriel.fr>
  14  *
  15  * SPDX-License-Identifier:     GPL-2.0+
  16  */
  17
  18 #include <common.h>
  19 #include <asm/arch/s3c2440.h>
  20 #include <asm/arch/iomux.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/io.h>
  23 #include <asm/gpio.h>
  24 #include <netdev.h>
  25 #include "mini2440.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 static inline void pll_delay(unsigned long loops)
  30 {
  31         __asm__ volatile ("1:\n"
  32           "subs %0, %1, #1\n"
  33           "bne 1b" : "=r" (loops) : "0" (loops));
  34 }
  35
  36 int board_early_init_f(void)
  37 {
  38         struct s3c24x0_clock_power * const clk_power =
  39                                         s3c24x0_get_base_clock_power();
  40
  41         /* to reduce PLL lock time, adjust the LOCKTIME register */
  42         clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
  43         clk_power->clkdivn = CLKDIVN_VAL;
  44
  45         /* configure UPLL */
  46         clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
  47         /* some delay between MPLL and UPLL */
  48         pll_delay(100);
  49
  50         /* configure MPLL */
  51         clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
  52
  53         /* some delay between MPLL and UPLL */
  54         pll_delay(10000);
  55
  56         return 0;
  57 }
  58
  59 /*
  60  * Miscellaneous platform dependent initialisations
  61  */
  62 int board_init(void)
  63 {
  64         struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
  65
  66         /* IOMUX Port H : UART Configuration */
  67         gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
  68                 IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
  69
  70         gpio_direction_output(GPH8, 0);
  71         gpio_direction_output(GPH9, 0);
  72         gpio_direction_output(GPH10, 0);
  73
  74         /* adress of boot parameters */
  75         gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
  76
  77         return 0;
  78 }
  79
  80 int dram_init(void)
  81 {
  82         struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
  83
  84         /*
  85          * Configuring bus width and timing
  86          * Initialize clocks for each bank 0..5
  87          * Bank 3 and 4 are used for DM9000
  88          */
  89         writel(BANK_CONF, &memctl->bwscon);
  90         writel(B0_CONF, &memctl->bankcon[0]);
  91         writel(B1_CONF, &memctl->bankcon[1]);
  92         writel(B2_CONF, &memctl->bankcon[2]);
  93         writel(B3_CONF, &memctl->bankcon[3]);
  94         writel(B4_CONF, &memctl->bankcon[4]);
  95         writel(B5_CONF, &memctl->bankcon[5]);
  96
  97         /* Bank 6 and 7 are used for DRAM */
  98         writel(SDRAM_64MB, &memctl->bankcon[6]);
  99         writel(SDRAM_64MB, &memctl->bankcon[7]);
 100
 101         writel(MEM_TIMING, &memctl->refresh);
 102         writel(BANKSIZE_CONF, &memctl->banksize);
 103         writel(B6_MRSR, &memctl->mrsrb6);
 104         writel(B7_MRSR, &memctl->mrsrb7);
 105
 106         gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
 107                         PHYS_SDRAM_SIZE);
 108         return 0;
 109 }
 110
 111 int board_eth_init(bd_t *bis)
 112 {
 113 #ifdef CONFIG_DRIVER_DM9000
 114         return dm9000_initialize(bis);
 115 #else
 116         return 0;
 117 #endif
 118 }