board/galaxy5200/galaxy5200.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2006
   9  * Eric Schumann, Phytec Messtechnik GmbH
  10  *
  11  * (C) Copyright 2009
  12  * Eric Millbrandt, DEKA Research and Development Corporation
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #include <common.h>
  18 #include <mpc5xxx.h>
  19 #include <pci.h>
  20 #include <asm/io.h>
  21
  22 #ifndef CONFIG_SYS_RAMBOOT
  23 static void sdram_start(int hi_addr)
  24 {
  25         volatile struct mpc5xxx_cdm *cdm =
  26                 (struct mpc5xxx_cdm *)MPC5XXX_CDM;
  27         volatile struct mpc5xxx_sdram *sdram =
  28                 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  29
  30         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  31
  32         /* unlock mode register */
  33         out_be32 (&sdram->ctrl,
  34                 (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
  35
  36         /* precharge all banks */
  37         out_be32 (&sdram->ctrl,
  38                 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
  39
  40 #ifdef SDRAM_DDR
  41         /* set mode register: extended mode */
  42         out_be32 (&sdram->mode, (SDRAM_EMODE));
  43
  44         /* set mode register: reset DLL */
  45         out_be32 (&sdram->mode, (SDRAM_MODE | 0x04000000));
  46 #endif
  47
  48         /* precharge all banks */
  49         out_be32 (&sdram->ctrl,
  50                 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
  51
  52         /* auto refresh */
  53         out_be32 (&sdram->ctrl,
  54                 (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
  55
  56         /* set mode register */
  57         out_be32 (&sdram->mode, (SDRAM_MODE));
  58
  59         /* normal operation */
  60         out_be32 (&sdram->ctrl,
  61                 (SDRAM_CONTROL | hi_addr_bit));
  62
  63         /* set CDM clock enable register, set MPC5200B SDRAM bus */
  64         /* to reduced driver strength */
  65         out_be32 (&cdm->clock_enable, (0x00CFFFFF));
  66 }
  67 #endif
  68
  69 /*
  70  * ATTENTION: Although partially referenced initdram does NOT make
  71  *      real use of CONFIG_SYS_SDRAM_BASE. The code does not
  72  *      work if CONFIG_SYS_SDRAM_BASE
  73  *      is something else than 0x00000000.
  74  */
  75
  76 phys_size_t initdram(int board_type)
  77 {
  78         volatile struct mpc5xxx_mmap_ctl *mm =
  79                 (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
  80         volatile struct mpc5xxx_sdram *sdram =
  81                 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  82         ulong dramsize = 0;
  83         ulong dramsize2 = 0;
  84 #ifndef CONFIG_SYS_RAMBOOT
  85         ulong test1, test2;
  86
  87         /* setup SDRAM chip selects */
  88                                                          /* 256MB at 0x0 */
  89         out_be32 (&mm->sdram0, 0x0000001b);
  90                                                          /* disabled */
  91         out_be32 (&mm->sdram1, 0x10000000);
  92
  93         /* setup config registers */
  94         out_be32 (&sdram->config1, SDRAM_CONFIG1);
  95         out_be32 (&sdram->config2, SDRAM_CONFIG2);
  96
  97         /* find RAM size using SDRAM CS0 only */
  98         sdram_start(0);
  99         test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
 100         sdram_start(1);
 101         test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
 102         if (test1 > test2) {
 103                 sdram_start(0);
 104                 dramsize = test1;
 105         } else
 106                 dramsize = test2;
 107
 108         /* memory smaller than 1MB is impossible */
 109         if (dramsize < (1 << 20))
 110                 dramsize = 0;
 111
 112         /* set SDRAM CS0 size according to the amount of RAM found */
 113         if (dramsize > 0) {
 114                 out_be32 (&mm->sdram0,
 115                         (0x13 + __builtin_ffs(dramsize >> 20) - 1));
 116         } else {
 117                                                         /* disabled */
 118                 out_be32 (&mm->sdram0, 0);
 119         }
 120
 121 #else /* CONFIG_SYS_RAMBOOT */
 122
 123         /* retrieve size of memory connected to SDRAM CS0 */
 124         dramsize = in_be32(&mm->sdram0) & 0xFF;
 125         if (dramsize >= 0x13)
 126                 dramsize = (1 << (dramsize - 0x13)) << 20;
 127         else
 128                 dramsize = 0;
 129
 130         /* retrieve size of memory connected to SDRAM CS1 */
 131         dramsize2 = in_be32(&mm->sdram1) & 0xFF;
 132         if (dramsize2 >= 0x13)
 133                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 134         else
 135                 dramsize2 = 0;
 136
 137 #endif /* CONFIG_SYS_RAMBOOT */
 138
 139         return dramsize + dramsize2;
 140 }
 141
 142 int checkboard(void)
 143 {
 144         puts("Board: galaxy5200\n");
 145         return 0;
 146 }
 147
 148 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 149 void ft_board_setup(void *blob, bd_t * bd)
 150 {
 151         ft_cpu_setup(blob, bd);
 152 }
 153 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 154
 155 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 156
 157 void init_ide_reset (void)
 158 {
 159         volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
 160         debug ("init_ide_reset\n");
 161
 162         /* Configure TIMER_5 as GPIO output for ATA reset */
 163         /* Deassert reset */
 164         gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
 165 }
 166
 167 void ide_set_reset (int idereset)
 168 {
 169         volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
 170         debug ("ide_reset(%d)\n", idereset);
 171
 172         /* Configure TIMER_5 as GPIO output for ATA reset */
 173         if (idereset) {
 174                 gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 | MPC5XXX_GPT_TMS_GPIO;
 175
 176                 /* Make a delay. MPC5200 spec says 25 usec min */
 177                 udelay(50);
 178         } else {
 179                 gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
 180                 udelay(50);
 181         }
 182 }
 183 #endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */