board/galaxy5200/galaxy5200.c

   1 /*
   2  * (C) Copyright 2003
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004
   6  * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7  *
   8  * (C) Copyright 2006
   9  * Eric Schumann, Phytec Messtechnik GmbH
  10  *
  11  * (C) Copyright 2009
  12  * Eric Millbrandt, DEKA Research and Development Corporation
  13  *
  14  * See file CREDITS for list of people who contributed to this
  15  * project.
  16  *
  17  * This program is free software; you can redistribute it and/or
  18  * modify it under the terms of the GNU General Public License as
  19  * published by the Free Software Foundation; either version 2 of
  20  * the License, or (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30  * MA 02111-1307 USA
  31  */
  32
  33 #include <common.h>
  34 #include <mpc5xxx.h>
  35 #include <pci.h>
  36 #include <asm/io.h>
  37
  38 #ifndef CONFIG_SYS_RAMBOOT
  39 static void sdram_start(int hi_addr)
  40 {
  41         volatile struct mpc5xxx_cdm *cdm =
  42                 (struct mpc5xxx_cdm *)MPC5XXX_CDM;
  43         volatile struct mpc5xxx_sdram *sdram =
  44                 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  45
  46         long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  47
  48         /* unlock mode register */
  49         out_be32 (&sdram->ctrl,
  50                 (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
  51
  52         /* precharge all banks */
  53         out_be32 (&sdram->ctrl,
  54                 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
  55
  56 #ifdef SDRAM_DDR
  57         /* set mode register: extended mode */
  58         out_be32 (&sdram->mode, (SDRAM_EMODE));
  59
  60         /* set mode register: reset DLL */
  61         out_be32 (&sdram->mode, (SDRAM_MODE | 0x04000000));
  62 #endif
  63
  64         /* precharge all banks */
  65         out_be32 (&sdram->ctrl,
  66                 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
  67
  68         /* auto refresh */
  69         out_be32 (&sdram->ctrl,
  70                 (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
  71
  72         /* set mode register */
  73         out_be32 (&sdram->mode, (SDRAM_MODE));
  74
  75         /* normal operation */
  76         out_be32 (&sdram->ctrl,
  77                 (SDRAM_CONTROL | hi_addr_bit));
  78
  79         /* set CDM clock enable register, set MPC5200B SDRAM bus */
  80         /* to reduced driver strength */
  81         out_be32 (&cdm->clock_enable, (0x00CFFFFF));
  82 }
  83 #endif
  84
  85 /*
  86  * ATTENTION: Although partially referenced initdram does NOT make
  87  *      real use of CONFIG_SYS_SDRAM_BASE. The code does not
  88  *      work if CONFIG_SYS_SDRAM_BASE
  89  *      is something else than 0x00000000.
  90  */
  91
  92 phys_size_t initdram(int board_type)
  93 {
  94         volatile struct mpc5xxx_mmap_ctl *mm =
  95                 (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
  96         volatile struct mpc5xxx_sdram *sdram =
  97                 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  98         ulong dramsize = 0;
  99         ulong dramsize2 = 0;
 100 #ifndef CONFIG_SYS_RAMBOOT
 101         ulong test1, test2;
 102
 103         /* setup SDRAM chip selects */
 104                                                          /* 256MB at 0x0 */
 105         out_be32 (&mm->sdram0, 0x0000001b);
 106                                                          /* disabled */
 107         out_be32 (&mm->sdram1, 0x10000000);
 108
 109         /* setup config registers */
 110         out_be32 (&sdram->config1, SDRAM_CONFIG1);
 111         out_be32 (&sdram->config2, SDRAM_CONFIG2);
 112
 113         /* find RAM size using SDRAM CS0 only */
 114         sdram_start(0);
 115         test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
 116         sdram_start(1);
 117         test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
 118         if (test1 > test2) {
 119                 sdram_start(0);
 120                 dramsize = test1;
 121         } else
 122                 dramsize = test2;
 123
 124         /* memory smaller than 1MB is impossible */
 125         if (dramsize < (1 << 20))
 126                 dramsize = 0;
 127
 128         /* set SDRAM CS0 size according to the amount of RAM found */
 129         if (dramsize > 0) {
 130                 out_be32 (&mm->sdram0,
 131                         (0x13 + __builtin_ffs(dramsize >> 20) - 1));
 132         } else {
 133                                                         /* disabled */
 134                 out_be32 (&mm->sdram0, 0);
 135         }
 136
 137 #else /* CONFIG_SYS_RAMBOOT */
 138
 139         /* retrieve size of memory connected to SDRAM CS0 */
 140         dramsize = in_be32(&mm->sdram0) & 0xFF;
 141         if (dramsize >= 0x13)
 142                 dramsize = (1 << (dramsize - 0x13)) << 20;
 143         else
 144                 dramsize = 0;
 145
 146         /* retrieve size of memory connected to SDRAM CS1 */
 147         dramsize2 = in_be32(&mm->sdram1) & 0xFF;
 148         if (dramsize2 >= 0x13)
 149                 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 150         else
 151                 dramsize2 = 0;
 152
 153 #endif /* CONFIG_SYS_RAMBOOT */
 154
 155         return dramsize + dramsize2;
 156 }
 157
 158 int checkboard(void)
 159 {
 160         puts("Board: galaxy5200\n");
 161         return 0;
 162 }
 163
 164 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 165 void ft_board_setup(void *blob, bd_t * bd)
 166 {
 167         ft_cpu_setup(blob, bd);
 168 }
 169 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 170
 171 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 172
 173 void init_ide_reset (void)
 174 {
 175         volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
 176         debug ("init_ide_reset\n");
 177
 178         /* Configure TIMER_5 as GPIO output for ATA reset */
 179         /* Deassert reset */
 180         gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
 181 }
 182
 183 void ide_set_reset (int idereset)
 184 {
 185         volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
 186         debug ("ide_reset(%d)\n", idereset);
 187
 188         /* Configure TIMER_5 as GPIO output for ATA reset */
 189         if (idereset) {
 190                 gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 | MPC5XXX_GPT_TMS_GPIO;
 191
 192                 /* Make a delay. MPC5200 spec says 25 usec min */
 193                 udelay(50);
 194         } else {
 195                 gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
 196                 udelay(50);
 197         }
 198 }
 199 #endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */