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git.ipfire.org Git - people/ms/u-boot.git/blob - board/gateworks/gw_ventana/gsc.c
2 * Copyright (C) 2013 Gateworks Corporation
4 * Author: Tim Harvey <tharvey@gateworks.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/ctype.h>
14 #include "ventana_eeprom.h"
18 * The Gateworks System Controller will fail to ACK a master transaction if
19 * it is busy, which can occur during its 1HZ timer tick while reading ADC's.
20 * When this does occur, it will never be busy long enough to fail more than
21 * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
24 int gsc_i2c_read(uchar chip
, uint addr
, int alen
, uchar
*buf
, int len
)
31 ret
= i2c_read(chip
, addr
, alen
, buf
, len
);
34 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__
, chip
, addr
,
43 int gsc_i2c_write(uchar chip
, uint addr
, int alen
, uchar
*buf
, int len
)
50 ret
= i2c_write(chip
, addr
, alen
, buf
, len
);
53 debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__
, chip
, addr
,
63 static void read_hwmon(const char *name
, uint reg
, uint size
)
68 printf("%-8s:", name
);
69 memset(buf
, 0, sizeof(buf
));
70 if (gsc_i2c_read(GSC_HWMON_ADDR
, reg
, 1, buf
, size
)) {
73 ui
= buf
[0] | (buf
[1]<<8) | (buf
[2]<<16);
74 if (reg
== GSC_HWMON_TEMP
&& ui
> 0x8000)
83 int gsc_info(int verbose
)
85 unsigned char buf
[16];
88 if (gsc_i2c_read(GSC_SC_ADDR
, 0, 1, buf
, 16))
89 return CMD_RET_FAILURE
;
91 printf("GSC: v%d", buf
[GSC_SC_FWVER
]);
92 printf(" 0x%04x", buf
[GSC_SC_FWCRC
] | buf
[GSC_SC_FWCRC
+1]<<8);
93 printf(" WDT:%sabled", (buf
[GSC_SC_CTRL1
] & (1<<GSC_SC_CTRL1_WDEN
))
95 if (buf
[GSC_SC_STATUS
] & (1 << GSC_SC_IRQ_WATCHDOG
)) {
96 buf
[GSC_SC_STATUS
] &= ~(1 << GSC_SC_IRQ_WATCHDOG
);
98 gsc_i2c_write(GSC_SC_ADDR
, GSC_SC_STATUS
, 1,
99 &buf
[GSC_SC_STATUS
], 1);
103 return CMD_RET_SUCCESS
;
105 read_hwmon("Temp", GSC_HWMON_TEMP
, 2);
106 read_hwmon("VIN", GSC_HWMON_VIN
, 3);
107 read_hwmon("VBATT", GSC_HWMON_VBATT
, 3);
108 read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3
, 3);
109 read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE
, 3);
110 read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC
, 3);
111 read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH
, 3);
112 read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR
, 3);
113 read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0
, 3);
114 read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5
, 3);
115 read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8
, 3);
116 read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2
, 3);
117 switch (ventana_info
.model
[3]) {
118 case '1': /* GW51xx */
119 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4
, 3); /* -C rev */
121 case '2': /* GW52xx */
123 case '3': /* GW53xx */
124 read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4
, 3); /* -C rev */
125 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3
, 3);
127 case '4': /* GW54xx */
128 read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4
, 3); /* -C rev */
129 read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3
, 3);
131 case '5': /* GW55xx */
138 * The Gateworks System Controller implements a boot
139 * watchdog (always enabled) as a workaround for IMX6 boot related
141 * ERR005768 - no fix scheduled
142 * ERR006282 - fixed in silicon r1.2
143 * ERR007117 - fixed in silicon r1.3
144 * ERR007220 - fixed in silicon r1.3
145 * ERR007926 - no fix scheduled
146 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
148 * Disable the boot watchdog
150 int gsc_boot_wd_disable(void)
154 i2c_set_bus_num(CONFIG_I2C_GSC
);
155 if (!gsc_i2c_read(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1)) {
156 reg
|= (1 << GSC_SC_CTRL1_WDDIS
);
157 if (!gsc_i2c_write(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1))
160 puts("Error: could not disable GSC Watchdog\n");
164 #ifdef CONFIG_CMD_GSC
165 static int do_gsc_sleep(cmd_tbl_t
*cmdtp
, int flag
, int argc
,
169 unsigned long secs
= 0;
172 return CMD_RET_USAGE
;
174 secs
= simple_strtoul(argv
[1], NULL
, 10);
175 printf("GSC Sleeping for %ld seconds\n", secs
);
178 reg
= (secs
>> 24) & 0xff;
179 if (gsc_i2c_write(GSC_SC_ADDR
, 9, 1, ®
, 1))
181 reg
= (secs
>> 16) & 0xff;
182 if (gsc_i2c_write(GSC_SC_ADDR
, 8, 1, ®
, 1))
184 reg
= (secs
>> 8) & 0xff;
185 if (gsc_i2c_write(GSC_SC_ADDR
, 7, 1, ®
, 1))
188 if (gsc_i2c_write(GSC_SC_ADDR
, 6, 1, ®
, 1))
190 if (gsc_i2c_read(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1))
193 if (gsc_i2c_write(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1))
197 if (gsc_i2c_write(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1))
200 return CMD_RET_SUCCESS
;
203 printf("i2c error\n");
204 return CMD_RET_FAILURE
;
207 static int do_gsc_wd(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
212 return CMD_RET_USAGE
;
214 if (strcasecmp(argv
[1], "enable") == 0) {
218 timeout
= simple_strtoul(argv
[2], NULL
, 10);
220 if (gsc_i2c_read(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1))
221 return CMD_RET_FAILURE
;
222 reg
&= ~((1 << GSC_SC_CTRL1_WDEN
) | (1 << GSC_SC_CTRL1_WDTIME
));
224 reg
|= (1 << GSC_SC_CTRL1_WDTIME
);
227 reg
|= (1 << GSC_SC_CTRL1_WDEN
);
228 if (gsc_i2c_write(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1))
229 return CMD_RET_FAILURE
;
230 printf("GSC Watchdog enabled with timeout=%d seconds\n",
232 } else if (strcasecmp(argv
[1], "disable") == 0) {
234 if (gsc_i2c_read(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1))
235 return CMD_RET_FAILURE
;
236 reg
&= ~((1 << GSC_SC_CTRL1_WDEN
) | (1 << GSC_SC_CTRL1_WDTIME
));
237 if (gsc_i2c_write(GSC_SC_ADDR
, GSC_SC_CTRL1
, 1, ®
, 1))
238 return CMD_RET_FAILURE
;
239 printf("GSC Watchdog disabled\n");
241 return CMD_RET_USAGE
;
243 return CMD_RET_SUCCESS
;
246 static int do_gsc(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
251 if (strcasecmp(argv
[1], "wd") == 0)
252 return do_gsc_wd(cmdtp
, flag
, --argc
, ++argv
);
253 else if (strcasecmp(argv
[1], "sleep") == 0)
254 return do_gsc_sleep(cmdtp
, flag
, --argc
, ++argv
);
256 return CMD_RET_USAGE
;
260 gsc
, 4, 1, do_gsc
, "GSC configuration",
261 "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
264 #endif /* CONFIG_CMD_GSC */