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imx: ventana: add 'gsc wd' command for enabling and disabling GSC watchdog
[people/ms/u-boot.git] / board / gateworks / gw_ventana / gw_ventana.c
1 /*
2 * Copyright (C) 2013 Gateworks Corporation
3 *
4 * Author: Tim Harvey <tharvey@gateworks.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/mxc_hdmi.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/gpio.h>
19 #include <asm/imx-common/iomux-v3.h>
20 #include <asm/imx-common/mxc_i2c.h>
21 #include <asm/imx-common/boot_mode.h>
22 #include <asm/imx-common/sata.h>
23 #include <asm/imx-common/spi.h>
24 #include <asm/imx-common/video.h>
25 #include <jffs2/load_kernel.h>
26 #include <hwconfig.h>
27 #include <i2c.h>
28 #include <linux/ctype.h>
29 #include <fdt_support.h>
30 #include <fsl_esdhc.h>
31 #include <miiphy.h>
32 #include <mmc.h>
33 #include <mtd_node.h>
34 #include <netdev.h>
35 #include <pci.h>
36 #include <power/pmic.h>
37 #include <power/ltc3676_pmic.h>
38 #include <power/pfuze100_pmic.h>
39 #include <fdt_support.h>
40 #include <jffs2/load_kernel.h>
41 #include <spi_flash.h>
42
43 #include "gsc.h"
44 #include "ventana_eeprom.h"
45
46 DECLARE_GLOBAL_DATA_PTR;
47
48 /* GPIO's common to all baseboards */
49 #define GP_PHY_RST IMX_GPIO_NR(1, 30)
50 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
51 #define GP_SD3_CD IMX_GPIO_NR(7, 0)
52 #define GP_RS232_EN IMX_GPIO_NR(2, 11)
53 #define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
54
55 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
57 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
58
59 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
60 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
61 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
62
63 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
64 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
65 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
66
67 #define SPI_PAD_CTRL (PAD_CTL_HYS | \
68 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
69 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
70
71 #define DIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
72 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
73 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
74
75 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
76 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
77 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
78
79 #define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
80 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
81 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
82
83 #define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION)
84
85
86 /*
87 * EEPROM board info struct populated by read_eeprom so that we only have to
88 * read it once.
89 */
90 struct ventana_board_info ventana_info;
91
92 static int board_type;
93
94 /* UART1: Function varies per baseboard */
95 static iomux_v3_cfg_t const uart1_pads[] = {
96 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
97 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
98 };
99
100 /* UART2: Serial Console */
101 static iomux_v3_cfg_t const uart2_pads[] = {
102 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
103 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
104 };
105
106 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
107
108 /* I2C1: GSC */
109 static struct i2c_pads_info mx6q_i2c_pad_info0 = {
110 .scl = {
111 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
112 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
113 .gp = IMX_GPIO_NR(3, 21)
114 },
115 .sda = {
116 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
117 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
118 .gp = IMX_GPIO_NR(3, 28)
119 }
120 };
121 static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
122 .scl = {
123 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
124 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
125 .gp = IMX_GPIO_NR(3, 21)
126 },
127 .sda = {
128 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
129 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
130 .gp = IMX_GPIO_NR(3, 28)
131 }
132 };
133
134 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
135 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
136 .scl = {
137 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
138 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
139 .gp = IMX_GPIO_NR(4, 12)
140 },
141 .sda = {
142 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
143 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
144 .gp = IMX_GPIO_NR(4, 13)
145 }
146 };
147 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
148 .scl = {
149 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
150 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
151 .gp = IMX_GPIO_NR(4, 12)
152 },
153 .sda = {
154 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
155 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
156 .gp = IMX_GPIO_NR(4, 13)
157 }
158 };
159
160 /* I2C3: Misc/Expansion */
161 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
162 .scl = {
163 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
164 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
165 .gp = IMX_GPIO_NR(1, 3)
166 },
167 .sda = {
168 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
169 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
170 .gp = IMX_GPIO_NR(1, 6)
171 }
172 };
173 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
174 .scl = {
175 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
176 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
177 .gp = IMX_GPIO_NR(1, 3)
178 },
179 .sda = {
180 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
181 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
182 .gp = IMX_GPIO_NR(1, 6)
183 }
184 };
185
186 /* MMC */
187 static iomux_v3_cfg_t const usdhc3_pads[] = {
188 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
189 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
190 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
191 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
192 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
193 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
194 /* CD */
195 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
196 };
197
198 /* ENET */
199 static iomux_v3_cfg_t const enet_pads[] = {
200 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
201 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
202 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
203 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
204 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
205 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
206 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
207 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
208 MUX_PAD_CTRL(ENET_PAD_CTRL)),
209 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
210 MUX_PAD_CTRL(ENET_PAD_CTRL)),
211 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
212 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
213 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
214 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
215 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
216 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
217 MUX_PAD_CTRL(ENET_PAD_CTRL)),
218 /* PHY nRST */
219 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
220 };
221
222 /* NAND */
223 static iomux_v3_cfg_t const nfc_pads[] = {
224 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
225 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
226 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
227 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
228 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
229 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
230 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
231 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
232 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
233 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
234 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
235 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
236 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
237 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
238 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
239 };
240
241 #ifdef CONFIG_CMD_NAND
242 static void setup_gpmi_nand(void)
243 {
244 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
245
246 /* config gpmi nand iomux */
247 SETUP_IOMUX_PADS(nfc_pads);
248
249 /* config gpmi and bch clock to 100 MHz */
250 clrsetbits_le32(&mxc_ccm->cs2cdr,
251 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
252 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
253 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
254 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
255 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
256 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
257
258 /* enable gpmi and bch clock gating */
259 setbits_le32(&mxc_ccm->CCGR4,
260 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
261 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
262 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
263 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
264 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
265
266 /* enable apbh clock gating */
267 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
268 }
269 #endif
270
271 static void setup_iomux_enet(void)
272 {
273 SETUP_IOMUX_PADS(enet_pads);
274
275 /* toggle PHY_RST# */
276 gpio_direction_output(GP_PHY_RST, 0);
277 mdelay(2);
278 gpio_set_value(GP_PHY_RST, 1);
279 }
280
281 static void setup_iomux_uart(void)
282 {
283 SETUP_IOMUX_PADS(uart1_pads);
284 SETUP_IOMUX_PADS(uart2_pads);
285 }
286
287 #ifdef CONFIG_USB_EHCI_MX6
288 static iomux_v3_cfg_t const usb_pads[] = {
289 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
290 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
291 /* OTG PWR */
292 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
293 };
294
295 int board_ehci_hcd_init(int port)
296 {
297 struct ventana_board_info *info = &ventana_info;
298
299 SETUP_IOMUX_PADS(usb_pads);
300
301 /* Reset USB HUB (present on GW54xx/GW53xx) */
302 switch (info->model[3]) {
303 case '3': /* GW53xx */
304 case '5': /* GW552x */
305 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG);
306 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
307 mdelay(2);
308 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
309 break;
310 case '4': /* GW54xx */
311 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG);
312 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
313 mdelay(2);
314 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
315 break;
316 }
317
318 return 0;
319 }
320
321 int board_ehci_power(int port, int on)
322 {
323 if (port)
324 return 0;
325 gpio_set_value(GP_USB_OTG_PWR, on);
326 return 0;
327 }
328 #endif /* CONFIG_USB_EHCI_MX6 */
329
330 #ifdef CONFIG_FSL_ESDHC
331 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
332
333 int board_mmc_getcd(struct mmc *mmc)
334 {
335 /* Card Detect */
336 gpio_direction_input(GP_SD3_CD);
337 return !gpio_get_value(GP_SD3_CD);
338 }
339
340 int board_mmc_init(bd_t *bis)
341 {
342 /* Only one USDHC controller on Ventana */
343 SETUP_IOMUX_PADS(usdhc3_pads);
344 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
345 usdhc_cfg.max_bus_width = 4;
346
347 return fsl_esdhc_initialize(bis, &usdhc_cfg);
348 }
349 #endif /* CONFIG_FSL_ESDHC */
350
351 #ifdef CONFIG_MXC_SPI
352 iomux_v3_cfg_t const ecspi1_pads[] = {
353 /* SS1 */
354 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
355 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
356 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
357 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
358 };
359
360 int board_spi_cs_gpio(unsigned bus, unsigned cs)
361 {
362 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
363 }
364
365 static void setup_spi(void)
366 {
367 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
368 SETUP_IOMUX_PADS(ecspi1_pads);
369 }
370 #endif
371
372 /* configure eth0 PHY board-specific LED behavior */
373 int board_phy_config(struct phy_device *phydev)
374 {
375 unsigned short val;
376
377 /* Marvel 88E1510 */
378 if (phydev->phy_id == 0x1410dd1) {
379 /*
380 * Page 3, Register 16: LED[2:0] Function Control Register
381 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
382 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
383 */
384 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
385 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
386 val &= 0xff00;
387 val |= 0x0017;
388 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
389 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
390 }
391
392 if (phydev->drv->config)
393 phydev->drv->config(phydev);
394
395 return 0;
396 }
397
398 int board_eth_init(bd_t *bis)
399 {
400 #ifdef CONFIG_FEC_MXC
401 if (board_type != GW551x && board_type != GW552x) {
402 setup_iomux_enet();
403 cpu_eth_init(bis);
404 }
405 #endif
406
407 #ifdef CONFIG_E1000
408 e1000_initialize(bis);
409 #endif
410
411 #ifdef CONFIG_CI_UDC
412 /* For otg ethernet*/
413 usb_eth_initialize(bis);
414 #endif
415
416 /* default to the first detected enet dev */
417 if (!getenv("ethprime")) {
418 struct eth_device *dev = eth_get_dev_by_index(0);
419 if (dev) {
420 setenv("ethprime", dev->name);
421 printf("set ethprime to %s\n", getenv("ethprime"));
422 }
423 }
424
425 return 0;
426 }
427
428 #if defined(CONFIG_VIDEO_IPUV3)
429
430 static void enable_hdmi(struct display_info_t const *dev)
431 {
432 imx_enable_hdmi_phy();
433 }
434
435 static int detect_i2c(struct display_info_t const *dev)
436 {
437 return i2c_set_bus_num(dev->bus) == 0 &&
438 i2c_probe(dev->addr) == 0;
439 }
440
441 static void enable_lvds(struct display_info_t const *dev)
442 {
443 struct iomuxc *iomux = (struct iomuxc *)
444 IOMUXC_BASE_ADDR;
445
446 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
447 u32 reg = readl(&iomux->gpr[2]);
448 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
449 writel(reg, &iomux->gpr[2]);
450
451 /* Enable Backlight */
452 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
453 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
454 }
455
456 struct display_info_t const displays[] = {{
457 /* HDMI Output */
458 .bus = -1,
459 .addr = 0,
460 .pixfmt = IPU_PIX_FMT_RGB24,
461 .detect = detect_hdmi,
462 .enable = enable_hdmi,
463 .mode = {
464 .name = "HDMI",
465 .refresh = 60,
466 .xres = 1024,
467 .yres = 768,
468 .pixclock = 15385,
469 .left_margin = 220,
470 .right_margin = 40,
471 .upper_margin = 21,
472 .lower_margin = 7,
473 .hsync_len = 60,
474 .vsync_len = 10,
475 .sync = FB_SYNC_EXT,
476 .vmode = FB_VMODE_NONINTERLACED
477 } }, {
478 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
479 .bus = 2,
480 .addr = 0x4,
481 .pixfmt = IPU_PIX_FMT_LVDS666,
482 .detect = detect_i2c,
483 .enable = enable_lvds,
484 .mode = {
485 .name = "Hannstar-XGA",
486 .refresh = 60,
487 .xres = 1024,
488 .yres = 768,
489 .pixclock = 15385,
490 .left_margin = 220,
491 .right_margin = 40,
492 .upper_margin = 21,
493 .lower_margin = 7,
494 .hsync_len = 60,
495 .vsync_len = 10,
496 .sync = FB_SYNC_EXT,
497 .vmode = FB_VMODE_NONINTERLACED
498 } }, {
499 /* DLC700JMG-T-4 */
500 .bus = 0,
501 .addr = 0,
502 .detect = NULL,
503 .enable = enable_lvds,
504 .pixfmt = IPU_PIX_FMT_LVDS666,
505 .mode = {
506 .name = "DLC700JMGT4",
507 .refresh = 60,
508 .xres = 1024, /* 1024x600active pixels */
509 .yres = 600,
510 .pixclock = 15385, /* 64MHz */
511 .left_margin = 220,
512 .right_margin = 40,
513 .upper_margin = 21,
514 .lower_margin = 7,
515 .hsync_len = 60,
516 .vsync_len = 10,
517 .sync = FB_SYNC_EXT,
518 .vmode = FB_VMODE_NONINTERLACED
519 } }, {
520 /* DLC800FIG-T-3 */
521 .bus = 0,
522 .addr = 0,
523 .detect = NULL,
524 .enable = enable_lvds,
525 .pixfmt = IPU_PIX_FMT_LVDS666,
526 .mode = {
527 .name = "DLC800FIGT3",
528 .refresh = 60,
529 .xres = 1024, /* 1024x768 active pixels */
530 .yres = 768,
531 .pixclock = 15385, /* 64MHz */
532 .left_margin = 220,
533 .right_margin = 40,
534 .upper_margin = 21,
535 .lower_margin = 7,
536 .hsync_len = 60,
537 .vsync_len = 10,
538 .sync = FB_SYNC_EXT,
539 .vmode = FB_VMODE_NONINTERLACED
540 } } };
541 size_t display_count = ARRAY_SIZE(displays);
542
543 static void setup_display(void)
544 {
545 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
546 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
547 int reg;
548
549 enable_ipu_clock();
550 imx_setup_hdmi();
551 /* Turn on LDB0,IPU,IPU DI0 clocks */
552 reg = __raw_readl(&mxc_ccm->CCGR3);
553 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
554 writel(reg, &mxc_ccm->CCGR3);
555
556 /* set LDB0, LDB1 clk select to 011/011 */
557 reg = readl(&mxc_ccm->cs2cdr);
558 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
559 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
560 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
561 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
562 writel(reg, &mxc_ccm->cs2cdr);
563
564 reg = readl(&mxc_ccm->cscmr2);
565 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
566 writel(reg, &mxc_ccm->cscmr2);
567
568 reg = readl(&mxc_ccm->chsccdr);
569 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
570 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
571 writel(reg, &mxc_ccm->chsccdr);
572
573 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
574 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
575 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
576 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
577 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
578 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
579 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
580 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
581 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
582 writel(reg, &iomux->gpr[2]);
583
584 reg = readl(&iomux->gpr[3]);
585 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
586 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
587 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
588 writel(reg, &iomux->gpr[3]);
589
590 /* Backlight CABEN on LVDS connector */
591 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
592 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
593 }
594 #endif /* CONFIG_VIDEO_IPUV3 */
595
596 /*
597 * Baseboard specific GPIO
598 */
599
600 /* common to add baseboards */
601 static iomux_v3_cfg_t const gw_gpio_pads[] = {
602 /* MSATA_EN */
603 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
604 /* RS232_EN# */
605 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
606 };
607
608 /* prototype */
609 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
610 /* PANLEDG# */
611 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
612 /* PANLEDR# */
613 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
614 /* LOCLED# */
615 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
616 /* RS485_EN */
617 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
618 /* IOEXP_PWREN# */
619 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
620 /* IOEXP_IRQ# */
621 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
622 /* VID_EN */
623 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
624 /* DIOI2C_DIS# */
625 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
626 /* PCICK_SSON */
627 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG),
628 /* PCI_RST# */
629 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
630 };
631
632 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
633 /* PANLEDG# */
634 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
635 /* PANLEDR# */
636 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
637 /* IOEXP_PWREN# */
638 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
639 /* IOEXP_IRQ# */
640 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
641
642 /* GPS_SHDN */
643 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
644 /* VID_PWR */
645 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
646 /* PCI_RST# */
647 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
648 /* PCIESKT_WDIS# */
649 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
650 };
651
652 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
653 /* PANLEDG# */
654 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
655 /* PANLEDR# */
656 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
657 /* IOEXP_PWREN# */
658 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
659 /* IOEXP_IRQ# */
660 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
661
662 /* MX6_LOCLED# */
663 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
664 /* GPS_SHDN */
665 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
666 /* USBOTG_SEL */
667 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
668 /* VID_PWR */
669 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
670 /* PCI_RST# */
671 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
672 /* PCIESKT_WDIS# */
673 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
674 };
675
676 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
677 /* PANLEDG# */
678 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
679 /* PANLEDR# */
680 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
681 /* MX6_LOCLED# */
682 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
683 /* IOEXP_PWREN# */
684 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
685 /* IOEXP_IRQ# */
686 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
687 /* DIOI2C_DIS# */
688 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
689 /* GPS_SHDN */
690 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
691 /* VID_EN */
692 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
693 /* PCI_RST# */
694 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
695 /* PCIESKT_WDIS# */
696 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
697 };
698
699 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
700 /* PANLEDG# */
701 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
702 /* PANLEDR# */
703 IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG),
704 /* MX6_LOCLED# */
705 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
706 /* MIPI_DIO */
707 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
708 /* RS485_EN */
709 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
710 /* IOEXP_PWREN# */
711 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
712 /* IOEXP_IRQ# */
713 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
714 /* DIOI2C_DIS# */
715 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
716 /* PCI_RST# */
717 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
718 /* VID_EN */
719 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
720 /* PCIESKT_WDIS# */
721 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
722 };
723
724 static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
725 /* PANLED# */
726 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
727 /* PCI_RST# */
728 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
729 /* PCIESKT_WDIS# */
730 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
731 };
732
733 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
734 /* PANLEDG# */
735 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
736 /* PANLEDR# */
737 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
738 /* MX6_LOCLED# */
739 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG),
740 /* PCI_RST# */
741 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG),
742 /* MX6_DIO[4:9] */
743 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
744 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
745 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
746 IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
747 IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
748 IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
749 /* PCIEGBE1_OFF# */
750 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
751 /* PCIEGBE2_OFF# */
752 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
753 /* PCIESKT_WDIS# */
754 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
755 };
756
757 /*
758 * each baseboard has 4 user configurable Digital IO lines which can
759 * be pinmuxed as a GPIO or in some cases a PWM
760 */
761 struct dio_cfg {
762 iomux_v3_cfg_t gpio_padmux[2];
763 unsigned gpio_param;
764 iomux_v3_cfg_t pwm_padmux[2];
765 unsigned pwm_param;
766 };
767
768 struct ventana {
769 /* pinmux */
770 iomux_v3_cfg_t const *gpio_pads;
771 int num_pads;
772 /* DIO pinmux/val */
773 struct dio_cfg dio_cfg[4];
774 int num_gpios;
775 /* various gpios (0 if non-existent) */
776 int leds[3];
777 int pcie_rst;
778 int mezz_pwren;
779 int mezz_irq;
780 int rs485en;
781 int gps_shdn;
782 int vidin_en;
783 int dioi2c_en;
784 int pcie_sson;
785 int usb_sel;
786 int wdis;
787 };
788
789 static struct ventana gpio_cfg[] = {
790 /* GW5400proto */
791 {
792 .gpio_pads = gw54xx_gpio_pads,
793 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
794 .dio_cfg = {
795 {
796 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
797 IMX_GPIO_NR(1, 9),
798 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
799 1
800 },
801 {
802 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
803 IMX_GPIO_NR(1, 19),
804 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
805 2
806 },
807 {
808 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
809 IMX_GPIO_NR(2, 9),
810 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
811 3
812 },
813 {
814 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
815 IMX_GPIO_NR(2, 10),
816 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
817 4
818 },
819 },
820 .num_gpios = 4,
821 .leds = {
822 IMX_GPIO_NR(4, 6),
823 IMX_GPIO_NR(4, 10),
824 IMX_GPIO_NR(4, 15),
825 },
826 .pcie_rst = IMX_GPIO_NR(1, 29),
827 .mezz_pwren = IMX_GPIO_NR(4, 7),
828 .mezz_irq = IMX_GPIO_NR(4, 9),
829 .rs485en = IMX_GPIO_NR(3, 24),
830 .dioi2c_en = IMX_GPIO_NR(4, 5),
831 .pcie_sson = IMX_GPIO_NR(1, 20),
832 },
833
834 /* GW51xx */
835 {
836 .gpio_pads = gw51xx_gpio_pads,
837 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
838 .dio_cfg = {
839 {
840 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
841 IMX_GPIO_NR(1, 16),
842 { 0, 0 },
843 0
844 },
845 {
846 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
847 IMX_GPIO_NR(1, 19),
848 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
849 2
850 },
851 {
852 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
853 IMX_GPIO_NR(1, 17),
854 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
855 3
856 },
857 {
858 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
859 IMX_GPIO_NR(1, 18),
860 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
861 4
862 },
863 },
864 .num_gpios = 4,
865 .leds = {
866 IMX_GPIO_NR(4, 6),
867 IMX_GPIO_NR(4, 10),
868 },
869 .pcie_rst = IMX_GPIO_NR(1, 0),
870 .mezz_pwren = IMX_GPIO_NR(2, 19),
871 .mezz_irq = IMX_GPIO_NR(2, 18),
872 .gps_shdn = IMX_GPIO_NR(1, 2),
873 .vidin_en = IMX_GPIO_NR(5, 20),
874 .wdis = IMX_GPIO_NR(7, 12),
875 },
876
877 /* GW52xx */
878 {
879 .gpio_pads = gw52xx_gpio_pads,
880 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
881 .dio_cfg = {
882 {
883 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
884 IMX_GPIO_NR(1, 16),
885 { 0, 0 },
886 0
887 },
888 {
889 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
890 IMX_GPIO_NR(1, 19),
891 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
892 2
893 },
894 {
895 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
896 IMX_GPIO_NR(1, 17),
897 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
898 3
899 },
900 {
901 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
902 IMX_GPIO_NR(1, 20),
903 { 0, 0 },
904 0
905 },
906 },
907 .num_gpios = 4,
908 .leds = {
909 IMX_GPIO_NR(4, 6),
910 IMX_GPIO_NR(4, 7),
911 IMX_GPIO_NR(4, 15),
912 },
913 .pcie_rst = IMX_GPIO_NR(1, 29),
914 .mezz_pwren = IMX_GPIO_NR(2, 19),
915 .mezz_irq = IMX_GPIO_NR(2, 18),
916 .gps_shdn = IMX_GPIO_NR(1, 27),
917 .vidin_en = IMX_GPIO_NR(3, 31),
918 .usb_sel = IMX_GPIO_NR(1, 2),
919 .wdis = IMX_GPIO_NR(7, 12),
920 },
921
922 /* GW53xx */
923 {
924 .gpio_pads = gw53xx_gpio_pads,
925 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
926 .dio_cfg = {
927 {
928 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
929 IMX_GPIO_NR(1, 16),
930 { 0, 0 },
931 0
932 },
933 {
934 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
935 IMX_GPIO_NR(1, 19),
936 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
937 2
938 },
939 {
940 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
941 IMX_GPIO_NR(1, 17),
942 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
943 3
944 },
945 {
946 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
947 IMX_GPIO_NR(1, 20),
948 { 0, 0 },
949 0
950 },
951 },
952 .num_gpios = 4,
953 .leds = {
954 IMX_GPIO_NR(4, 6),
955 IMX_GPIO_NR(4, 7),
956 IMX_GPIO_NR(4, 15),
957 },
958 .pcie_rst = IMX_GPIO_NR(1, 29),
959 .mezz_pwren = IMX_GPIO_NR(2, 19),
960 .mezz_irq = IMX_GPIO_NR(2, 18),
961 .gps_shdn = IMX_GPIO_NR(1, 27),
962 .vidin_en = IMX_GPIO_NR(3, 31),
963 .wdis = IMX_GPIO_NR(7, 12),
964 },
965
966 /* GW54xx */
967 {
968 .gpio_pads = gw54xx_gpio_pads,
969 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
970 .dio_cfg = {
971 {
972 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
973 IMX_GPIO_NR(1, 9),
974 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
975 1
976 },
977 {
978 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
979 IMX_GPIO_NR(1, 19),
980 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
981 2
982 },
983 {
984 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
985 IMX_GPIO_NR(2, 9),
986 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
987 3
988 },
989 {
990 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
991 IMX_GPIO_NR(2, 10),
992 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
993 4
994 },
995 },
996 .num_gpios = 4,
997 .leds = {
998 IMX_GPIO_NR(4, 6),
999 IMX_GPIO_NR(4, 7),
1000 IMX_GPIO_NR(4, 15),
1001 },
1002 .pcie_rst = IMX_GPIO_NR(1, 29),
1003 .mezz_pwren = IMX_GPIO_NR(2, 19),
1004 .mezz_irq = IMX_GPIO_NR(2, 18),
1005 .rs485en = IMX_GPIO_NR(7, 1),
1006 .vidin_en = IMX_GPIO_NR(3, 31),
1007 .dioi2c_en = IMX_GPIO_NR(4, 5),
1008 .pcie_sson = IMX_GPIO_NR(1, 20),
1009 .wdis = IMX_GPIO_NR(5, 17),
1010 },
1011
1012 /* GW551x */
1013 {
1014 .gpio_pads = gw551x_gpio_pads,
1015 .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
1016 .dio_cfg = {
1017 {
1018 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
1019 IMX_GPIO_NR(1, 16),
1020 { 0, 0 },
1021 0
1022 },
1023 {
1024 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
1025 IMX_GPIO_NR(1, 19),
1026 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
1027 2
1028 },
1029 {
1030 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
1031 IMX_GPIO_NR(1, 17),
1032 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
1033 3
1034 },
1035 {
1036 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
1037 IMX_GPIO_NR(1, 18),
1038 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
1039 4
1040 },
1041 },
1042 .num_gpios = 2,
1043 .leds = {
1044 IMX_GPIO_NR(4, 7),
1045 },
1046 .pcie_rst = IMX_GPIO_NR(1, 0),
1047 .wdis = IMX_GPIO_NR(7, 12),
1048 },
1049
1050 /* GW552x */
1051 {
1052 .gpio_pads = gw552x_gpio_pads,
1053 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
1054 .dio_cfg = {
1055 {
1056 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
1057 IMX_GPIO_NR(1, 19),
1058 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
1059 2
1060 },
1061 {
1062 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
1063 IMX_GPIO_NR(1, 17),
1064 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
1065 3
1066 },
1067 },
1068 .num_gpios = 4,
1069 .leds = {
1070 IMX_GPIO_NR(4, 6),
1071 IMX_GPIO_NR(4, 7),
1072 IMX_GPIO_NR(4, 15),
1073 },
1074 .pcie_rst = IMX_GPIO_NR(1, 29),
1075 .wdis = IMX_GPIO_NR(7, 12),
1076 },
1077 };
1078
1079 /* setup board specific PMIC */
1080 int power_init_board(void)
1081 {
1082 struct pmic *p;
1083 u32 reg;
1084
1085 /* configure PFUZE100 PMIC */
1086 if (board_type == GW54xx || board_type == GW54proto) {
1087 power_pfuze100_init(CONFIG_I2C_PMIC);
1088 p = pmic_get("PFUZE100");
1089 if (p && !pmic_probe(p)) {
1090 pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
1091 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
1092
1093 /* Set VGEN1 to 1.5V and enable */
1094 pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
1095 reg &= ~(LDO_VOL_MASK);
1096 reg |= (LDOA_1_50V | LDO_EN);
1097 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1098
1099 /* Set SWBST to 5.0V and enable */
1100 pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
1101 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1102 reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
1103 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1104 }
1105 }
1106
1107 /* configure LTC3676 PMIC */
1108 else {
1109 power_ltc3676_init(CONFIG_I2C_PMIC);
1110 p = pmic_get("LTC3676_PMIC");
1111 if (p && !pmic_probe(p)) {
1112 puts("PMIC: LTC3676\n");
1113 /*
1114 * set board-specific scalar for max CPU frequency
1115 * per CPU based on the LDO enabled Operating Ranges
1116 * defined in the respective IMX6DQ and IMX6SDL
1117 * datasheets. The voltage resulting from the R1/R2
1118 * feedback inputs on Ventana is 1308mV. Note that this
1119 * is a bit shy of the Vmin of 1350mV in the datasheet
1120 * for LDO enabled mode but is as high as we can go.
1121 *
1122 * We will rely on an OS kernel driver to properly
1123 * regulate these per CPU operating point and use LDO
1124 * bypass mode when using the higher frequency
1125 * operating points to compensate as LDO bypass mode
1126 * allows the rails be 125mV lower.
1127 */
1128 /* mask PGOOD during SW1 transition */
1129 pmic_reg_write(p, LTC3676_DVB1B,
1130 0x1f | LTC3676_PGOOD_MASK);
1131 /* set SW1 (VDD_SOC) */
1132 pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
1133
1134 /* mask PGOOD during SW3 transition */
1135 pmic_reg_write(p, LTC3676_DVB3B,
1136 0x1f | LTC3676_PGOOD_MASK);
1137 /* set SW3 (VDD_ARM) */
1138 pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1139 }
1140 }
1141
1142 return 0;
1143 }
1144
1145 /* setup GPIO pinmux and default configuration per baseboard */
1146 static void setup_board_gpio(int board)
1147 {
1148 struct ventana_board_info *info = &ventana_info;
1149 const char *s;
1150 char arg[10];
1151 size_t len;
1152 int i;
1153 int quiet = simple_strtol(getenv("quiet"), NULL, 10);
1154
1155 if (board >= GW_UNKNOWN)
1156 return;
1157
1158 /* RS232_EN# */
1159 gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
1160
1161 /* MSATA Enable */
1162 if (is_cpu_type(MXC_CPU_MX6Q) &&
1163 test_bit(EECONFIG_SATA, info->config)) {
1164 gpio_direction_output(GP_MSATA_SEL,
1165 (hwconfig("msata")) ? 1 : 0);
1166 } else {
1167 gpio_direction_output(GP_MSATA_SEL, 0);
1168 }
1169
1170 #if !defined(CONFIG_CMD_PCI)
1171 /* assert PCI_RST# (released by OS when clock is valid) */
1172 gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
1173 #endif
1174
1175 /* turn off (active-high) user LED's */
1176 for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) {
1177 if (gpio_cfg[board].leds[i])
1178 gpio_direction_output(gpio_cfg[board].leds[i], 1);
1179 }
1180
1181 /* Expansion Mezzanine IO */
1182 if (gpio_cfg[board].mezz_pwren)
1183 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1184 if (gpio_cfg[board].mezz_irq)
1185 gpio_direction_input(gpio_cfg[board].mezz_irq);
1186
1187 /* RS485 Transmit Enable */
1188 if (gpio_cfg[board].rs485en)
1189 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1190
1191 /* GPS_SHDN */
1192 if (gpio_cfg[board].gps_shdn)
1193 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1194
1195 /* Analog video codec power enable */
1196 if (gpio_cfg[board].vidin_en)
1197 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1198
1199 /* DIOI2C_DIS# */
1200 if (gpio_cfg[board].dioi2c_en)
1201 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1202
1203 /* PCICK_SSON: disable spread-spectrum clock */
1204 if (gpio_cfg[board].pcie_sson)
1205 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1206
1207 /* USBOTG Select (PCISKT or FrontPanel) */
1208 if (gpio_cfg[board].usb_sel)
1209 gpio_direction_output(gpio_cfg[board].usb_sel,
1210 (hwconfig("usb_pcisel")) ? 1 : 0);
1211
1212
1213 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1214 if (gpio_cfg[board].wdis)
1215 gpio_direction_output(gpio_cfg[board].wdis, 1);
1216
1217 /*
1218 * Configure DIO pinmux/padctl registers
1219 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1220 */
1221 for (i = 0; i < 4; i++) {
1222 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1223 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1224 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1225
1226 if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
1227 continue;
1228 sprintf(arg, "dio%d", i);
1229 if (!hwconfig(arg))
1230 continue;
1231 s = hwconfig_subarg(arg, "padctrl", &len);
1232 if (s) {
1233 ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16)
1234 & 0x1ffff) | MUX_MODE_SION;
1235 }
1236 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1237 if (!quiet) {
1238 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
1239 (cfg->gpio_param/32)+1,
1240 cfg->gpio_param%32,
1241 cfg->gpio_param);
1242 }
1243 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1244 ctrl);
1245 gpio_direction_input(cfg->gpio_param);
1246 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1247 cfg->pwm_padmux) {
1248 if (!quiet)
1249 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
1250 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1251 MUX_PAD_CTRL(ctrl));
1252 }
1253 }
1254
1255 if (!quiet) {
1256 if (is_cpu_type(MXC_CPU_MX6Q) &&
1257 (test_bit(EECONFIG_SATA, info->config))) {
1258 printf("MSATA: %s\n", (hwconfig("msata") ?
1259 "enabled" : "disabled"));
1260 }
1261 printf("RS232: %s\n", (hwconfig("rs232")) ?
1262 "enabled" : "disabled");
1263 }
1264 }
1265
1266 #if defined(CONFIG_CMD_PCI)
1267 int imx6_pcie_toggle_reset(void)
1268 {
1269 if (board_type < GW_UNKNOWN) {
1270 uint pin = gpio_cfg[board_type].pcie_rst;
1271 gpio_direction_output(pin, 0);
1272 mdelay(50);
1273 gpio_direction_output(pin, 1);
1274 }
1275 return 0;
1276 }
1277
1278 /*
1279 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
1280 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
1281 * properly and assert reset for 100ms.
1282 */
1283 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
1284 unsigned short vendor, unsigned short device,
1285 unsigned short class)
1286 {
1287 u32 dw;
1288
1289 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
1290 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
1291 if (vendor == PCI_VENDOR_ID_PLX &&
1292 (device & 0xfff0) == 0x8600 &&
1293 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
1294 debug("configuring PLX 860X downstream PERST#\n");
1295 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
1296 dw |= 0xaaa8; /* GPIO1-7 outputs */
1297 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
1298
1299 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
1300 dw |= 0xfe; /* GPIO1-7 output high */
1301 pci_hose_write_config_dword(hose, dev, 0x644, dw);
1302
1303 mdelay(100);
1304 }
1305 }
1306 #endif /* CONFIG_CMD_PCI */
1307
1308 #ifdef CONFIG_SERIAL_TAG
1309 /*
1310 * called when setting up ATAGS before booting kernel
1311 * populate serialnum from the following (in order of priority):
1312 * serial# env var
1313 * eeprom
1314 */
1315 void get_board_serial(struct tag_serialnr *serialnr)
1316 {
1317 char *serial = getenv("serial#");
1318
1319 if (serial) {
1320 serialnr->high = 0;
1321 serialnr->low = simple_strtoul(serial, NULL, 10);
1322 } else if (ventana_info.model[0]) {
1323 serialnr->high = 0;
1324 serialnr->low = ventana_info.serial;
1325 } else {
1326 serialnr->high = 0;
1327 serialnr->low = 0;
1328 }
1329 }
1330 #endif
1331
1332 /*
1333 * Board Support
1334 */
1335
1336 /* called from SPL board_init_f() */
1337 int board_early_init_f(void)
1338 {
1339 setup_iomux_uart();
1340 gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1341
1342 #if defined(CONFIG_VIDEO_IPUV3)
1343 setup_display();
1344 #endif
1345 return 0;
1346 }
1347
1348 int dram_init(void)
1349 {
1350 gd->ram_size = imx_ddr_size();
1351 return 0;
1352 }
1353
1354 int board_init(void)
1355 {
1356 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1357
1358 clrsetbits_le32(&iomuxc_regs->gpr[1],
1359 IOMUXC_GPR1_OTG_ID_MASK,
1360 IOMUXC_GPR1_OTG_ID_GPIO1);
1361
1362 /* address of linux boot parameters */
1363 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1364
1365 #ifdef CONFIG_CMD_NAND
1366 setup_gpmi_nand();
1367 #endif
1368 #ifdef CONFIG_MXC_SPI
1369 setup_spi();
1370 #endif
1371 if (is_cpu_type(MXC_CPU_MX6Q)) {
1372 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1373 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1374 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1375 } else {
1376 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1377 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1378 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1379 }
1380
1381 #ifdef CONFIG_CMD_SATA
1382 setup_sata();
1383 #endif
1384 /* read Gateworks EEPROM into global struct (used later) */
1385 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1386
1387 /* board-specifc GPIO iomux */
1388 SETUP_IOMUX_PADS(gw_gpio_pads);
1389 if (board_type < GW_UNKNOWN) {
1390 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1391 int count = gpio_cfg[board_type].num_pads;
1392
1393 imx_iomux_v3_setup_multiple_pads(p, count);
1394 }
1395
1396 return 0;
1397 }
1398
1399 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1400 /*
1401 * called during late init (after relocation and after board_init())
1402 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1403 * EEPROM read.
1404 */
1405 int checkboard(void)
1406 {
1407 struct ventana_board_info *info = &ventana_info;
1408 unsigned char buf[4];
1409 const char *p;
1410 int quiet; /* Quiet or minimal output mode */
1411
1412 quiet = 0;
1413 p = getenv("quiet");
1414 if (p)
1415 quiet = simple_strtol(p, NULL, 10);
1416 else
1417 setenv("quiet", "0");
1418
1419 puts("\nGateworks Corporation Copyright 2014\n");
1420 if (info->model[0]) {
1421 printf("Model: %s\n", info->model);
1422 printf("MFGDate: %02x-%02x-%02x%02x\n",
1423 info->mfgdate[0], info->mfgdate[1],
1424 info->mfgdate[2], info->mfgdate[3]);
1425 printf("Serial:%d\n", info->serial);
1426 } else {
1427 puts("Invalid EEPROM - board will not function fully\n");
1428 }
1429 if (quiet)
1430 return 0;
1431
1432 /* Display GSC firmware revision/CRC/status */
1433 gsc_info(0);
1434
1435 /* Display RTC */
1436 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1437 printf("RTC: %d\n",
1438 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1439 }
1440
1441 return 0;
1442 }
1443 #endif
1444
1445 #ifdef CONFIG_CMD_BMODE
1446 /*
1447 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1448 * see Table 8-11 and Table 5-9
1449 * BOOT_CFG1[7] = 1 (boot from NAND)
1450 * BOOT_CFG1[5] = 0 - raw NAND
1451 * BOOT_CFG1[4] = 0 - default pad settings
1452 * BOOT_CFG1[3:2] = 00 - devices = 1
1453 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1454 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1455 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1456 * BOOT_CFG2[0] = 0 - Reset time 12ms
1457 */
1458 static const struct boot_mode board_boot_modes[] = {
1459 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1460 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1461 { NULL, 0 },
1462 };
1463 #endif
1464
1465 /* late init */
1466 int misc_init_r(void)
1467 {
1468 struct ventana_board_info *info = &ventana_info;
1469 unsigned char reg;
1470
1471 /* set env vars based on EEPROM data */
1472 if (ventana_info.model[0]) {
1473 char str[16], fdt[36];
1474 char *p;
1475 const char *cputype = "";
1476 int i;
1477
1478 /*
1479 * FDT name will be prefixed with CPU type. Three versions
1480 * will be created each increasingly generic and bootloader
1481 * env scripts will try loading each from most specific to
1482 * least.
1483 */
1484 if (is_cpu_type(MXC_CPU_MX6Q) ||
1485 is_cpu_type(MXC_CPU_MX6D))
1486 cputype = "imx6q";
1487 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1488 is_cpu_type(MXC_CPU_MX6SOLO))
1489 cputype = "imx6dl";
1490 setenv("soctype", cputype);
1491 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1492 setenv("flash_layout", "large");
1493 else
1494 setenv("flash_layout", "normal");
1495 memset(str, 0, sizeof(str));
1496 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1497 str[i] = tolower(info->model[i]);
1498 if (!getenv("model"))
1499 setenv("model", str);
1500 if (!getenv("fdt_file")) {
1501 sprintf(fdt, "%s-%s.dtb", cputype, str);
1502 setenv("fdt_file", fdt);
1503 }
1504 p = strchr(str, '-');
1505 if (p) {
1506 *p++ = 0;
1507
1508 setenv("model_base", str);
1509 if (!getenv("fdt_file1")) {
1510 sprintf(fdt, "%s-%s.dtb", cputype, str);
1511 setenv("fdt_file1", fdt);
1512 }
1513 if (board_type != GW551x && board_type != GW552x)
1514 str[4] = 'x';
1515 str[5] = 'x';
1516 str[6] = 0;
1517 if (!getenv("fdt_file2")) {
1518 sprintf(fdt, "%s-%s.dtb", cputype, str);
1519 setenv("fdt_file2", fdt);
1520 }
1521 }
1522
1523 /* initialize env from EEPROM */
1524 if (test_bit(EECONFIG_ETH0, info->config) &&
1525 !getenv("ethaddr")) {
1526 eth_setenv_enetaddr("ethaddr", info->mac0);
1527 }
1528 if (test_bit(EECONFIG_ETH1, info->config) &&
1529 !getenv("eth1addr")) {
1530 eth_setenv_enetaddr("eth1addr", info->mac1);
1531 }
1532
1533 /* board serial-number */
1534 sprintf(str, "%6d", info->serial);
1535 setenv("serial#", str);
1536
1537 /* memory MB */
1538 sprintf(str, "%d", (int) (gd->ram_size >> 20));
1539 setenv("mem_mb", str);
1540 }
1541
1542
1543 /* setup baseboard specific GPIO pinmux and config */
1544 setup_board_gpio(board_type);
1545
1546 #ifdef CONFIG_CMD_BMODE
1547 add_board_boot_modes(board_boot_modes);
1548 #endif
1549
1550 /*
1551 * The Gateworks System Controller implements a boot
1552 * watchdog (always enabled) as a workaround for IMX6 boot related
1553 * errata such as:
1554 * ERR005768 - no fix scheduled
1555 * ERR006282 - fixed in silicon r1.2
1556 * ERR007117 - fixed in silicon r1.3
1557 * ERR007220 - fixed in silicon r1.3
1558 * ERR007926 - no fix scheduled
1559 * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1560 *
1561 * Disable the boot watchdog and display/clear the timeout flag if set
1562 */
1563 i2c_set_bus_num(CONFIG_I2C_GSC);
1564 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1565 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1566 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1567 puts("Error: could not disable GSC Watchdog\n");
1568 } else {
1569 puts("Error: could not disable GSC Watchdog\n");
1570 }
1571
1572 return 0;
1573 }
1574
1575 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1576
1577 /*
1578 * called prior to booting kernel or by 'fdt boardsetup' command
1579 *
1580 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1581 * - mtd partitions based on mtdparts/mtdids env
1582 * - system-serial (board serial num from EEPROM)
1583 * - board (full model from EEPROM)
1584 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1585 */
1586 int ft_board_setup(void *blob, bd_t *bd)
1587 {
1588 struct ventana_board_info *info = &ventana_info;
1589 struct ventana_eeprom_config *cfg;
1590 struct node_info nodes[] = {
1591 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1592 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1593 };
1594 const char *model = getenv("model");
1595 const char *display = getenv("display");
1596 int i;
1597 char rev = 0;
1598
1599 /* determine board revision */
1600 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1601 if (ventana_info.model[i] >= 'A') {
1602 rev = ventana_info.model[i];
1603 break;
1604 }
1605 }
1606
1607 if (getenv("fdt_noauto")) {
1608 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1609 return 0;
1610 }
1611
1612 /* Update partition nodes using info from mtdparts env var */
1613 puts(" Updating MTD partitions...\n");
1614 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1615
1616 /* Update display timings from display env var */
1617 if (display) {
1618 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1619 display) >= 0)
1620 printf(" Set display timings for %s...\n", display);
1621 }
1622
1623 if (!model) {
1624 puts("invalid board info: Leaving FDT fully enabled\n");
1625 return 0;
1626 }
1627 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1628
1629 /* board serial number */
1630 fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1631 strlen(getenv("serial#")) + 1);
1632
1633 /* board (model contains model from device-tree) */
1634 fdt_setprop(blob, 0, "board", info->model,
1635 strlen((const char *)info->model) + 1);
1636
1637 /*
1638 * disable serial2 node for GW54xx for compatibility with older
1639 * 3.10.x kernel that improperly had this node enabled in the DT
1640 */
1641 if (board_type == GW54xx) {
1642 i = fdt_path_offset(blob,
1643 "/soc/aips-bus@02100000/serial@021ec000");
1644 if (i)
1645 fdt_del_node(blob, i);
1646 }
1647
1648 /*
1649 * disable wdog1/wdog2 nodes for GW51xx below revC to work around
1650 * errata causing wdog timer to be unreliable.
1651 */
1652 if (board_type == GW51xx && rev >= 'A' && rev < 'C') {
1653 i = fdt_path_offset(blob,
1654 "/soc/aips-bus@02000000/wdog@020bc000");
1655 if (i)
1656 fdt_status_disabled(blob, i);
1657 }
1658
1659 /*
1660 * isolate CSI0_DATA_EN for GW551x below revB to work around
1661 * errata causing non functional digital video in (it is not hooked up)
1662 */
1663 else if (board_type == GW551x && rev == 'A') {
1664 u32 *range = NULL;
1665 int len;
1666 const u32 *handle = NULL;
1667
1668 i = fdt_node_offset_by_compatible(blob, -1,
1669 "fsl,imx-tda1997x-video");
1670 if (i)
1671 handle = fdt_getprop(blob, i, "pinctrl-0", NULL);
1672 if (handle)
1673 i = fdt_node_offset_by_phandle(blob,
1674 fdt32_to_cpu(*handle));
1675 if (i)
1676 range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len);
1677 if (range) {
1678 len /= sizeof(u32);
1679 for (i = 0; i < len; i += 6) {
1680 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1681 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1682 /* mux PAD_CSI0_DATA_EN to GPIO */
1683 if (is_cpu_type(MXC_CPU_MX6Q) &&
1684 mux_reg == 0x260 && conf_reg == 0x630)
1685 range[i+3] = cpu_to_fdt32(0x5);
1686 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1687 mux_reg == 0x08c && conf_reg == 0x3a0)
1688 range[i+3] = cpu_to_fdt32(0x5);
1689 }
1690 fdt_setprop_inplace(blob, i, "fsl,pins", range, len);
1691 }
1692 }
1693
1694 /*
1695 * Peripheral Config:
1696 * remove nodes by alias path if EEPROM config tells us the
1697 * peripheral is not loaded on the board.
1698 */
1699 if (getenv("fdt_noconfig")) {
1700 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1701 return 0;
1702 }
1703 cfg = econfig;
1704 while (cfg->name) {
1705 if (!test_bit(cfg->bit, info->config)) {
1706 fdt_del_node_and_alias(blob, cfg->dtalias ?
1707 cfg->dtalias : cfg->name);
1708 }
1709 cfg++;
1710 }
1711
1712 return 0;
1713 }
1714 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1715
"Das U-Boot" Source Tree