2 * Copyright (C) 2014 Gateworks Corporation
3 * Author: Tim Harvey <tharvey@gateworks.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6-ddr.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/imx-common/boot_mode.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/mxc_i2c.h>
22 DECLARE_GLOBAL_DATA_PTR
;
24 #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
25 #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
26 #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
28 /* configure MX6Q/DUAL mmdc DDR io registers */
29 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs
= {
30 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
31 .dram_sdclk_0
= 0x00020030,
32 .dram_sdclk_1
= 0x00020030,
33 .dram_cas
= 0x00020030,
34 .dram_ras
= 0x00020030,
35 .dram_reset
= 0x00020030,
36 /* SDCKE[0:1]: 100k pull-up */
37 .dram_sdcke0
= 0x00003000,
38 .dram_sdcke1
= 0x00003000,
39 /* SDBA2: pull-up disabled */
40 .dram_sdba2
= 0x00000000,
41 /* SDODT[0:1]: 100k pull-up, 40 ohm */
42 .dram_sdodt0
= 0x00003030,
43 .dram_sdodt1
= 0x00003030,
44 /* SDQS[0:7]: Differential input, 40 ohm */
45 .dram_sdqs0
= 0x00000030,
46 .dram_sdqs1
= 0x00000030,
47 .dram_sdqs2
= 0x00000030,
48 .dram_sdqs3
= 0x00000030,
49 .dram_sdqs4
= 0x00000030,
50 .dram_sdqs5
= 0x00000030,
51 .dram_sdqs6
= 0x00000030,
52 .dram_sdqs7
= 0x00000030,
54 /* DQM[0:7]: Differential input, 40 ohm */
55 .dram_dqm0
= 0x00020030,
56 .dram_dqm1
= 0x00020030,
57 .dram_dqm2
= 0x00020030,
58 .dram_dqm3
= 0x00020030,
59 .dram_dqm4
= 0x00020030,
60 .dram_dqm5
= 0x00020030,
61 .dram_dqm6
= 0x00020030,
62 .dram_dqm7
= 0x00020030,
65 /* configure MX6Q/DUAL mmdc GRP io registers */
66 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs
= {
68 .grp_ddr_type
= 0x000c0000,
69 .grp_ddrmode_ctl
= 0x00020000,
70 /* disable DDR pullups */
71 .grp_ddrpke
= 0x00000000,
72 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
73 .grp_addds
= 0x00000030,
74 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
75 .grp_ctlds
= 0x00000030,
76 /* DATA[00:63]: Differential input, 40 ohm */
77 .grp_ddrmode
= 0x00020000,
78 .grp_b0ds
= 0x00000030,
79 .grp_b1ds
= 0x00000030,
80 .grp_b2ds
= 0x00000030,
81 .grp_b3ds
= 0x00000030,
82 .grp_b4ds
= 0x00000030,
83 .grp_b5ds
= 0x00000030,
84 .grp_b6ds
= 0x00000030,
85 .grp_b7ds
= 0x00000030,
88 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
89 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs
= {
90 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
91 .dram_sdclk_0
= 0x00020030,
92 .dram_sdclk_1
= 0x00020030,
93 .dram_cas
= 0x00020030,
94 .dram_ras
= 0x00020030,
95 .dram_reset
= 0x00020030,
96 /* SDCKE[0:1]: 100k pull-up */
97 .dram_sdcke0
= 0x00003000,
98 .dram_sdcke1
= 0x00003000,
99 /* SDBA2: pull-up disabled */
100 .dram_sdba2
= 0x00000000,
101 /* SDODT[0:1]: 100k pull-up, 40 ohm */
102 .dram_sdodt0
= 0x00003030,
103 .dram_sdodt1
= 0x00003030,
104 /* SDQS[0:7]: Differential input, 40 ohm */
105 .dram_sdqs0
= 0x00000030,
106 .dram_sdqs1
= 0x00000030,
107 .dram_sdqs2
= 0x00000030,
108 .dram_sdqs3
= 0x00000030,
109 .dram_sdqs4
= 0x00000030,
110 .dram_sdqs5
= 0x00000030,
111 .dram_sdqs6
= 0x00000030,
112 .dram_sdqs7
= 0x00000030,
114 /* DQM[0:7]: Differential input, 40 ohm */
115 .dram_dqm0
= 0x00020030,
116 .dram_dqm1
= 0x00020030,
117 .dram_dqm2
= 0x00020030,
118 .dram_dqm3
= 0x00020030,
119 .dram_dqm4
= 0x00020030,
120 .dram_dqm5
= 0x00020030,
121 .dram_dqm6
= 0x00020030,
122 .dram_dqm7
= 0x00020030,
125 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
126 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs
= {
128 .grp_ddr_type
= 0x000c0000,
129 /* SDQS[0:7]: Differential input, 40 ohm */
130 .grp_ddrmode_ctl
= 0x00020000,
131 /* disable DDR pullups */
132 .grp_ddrpke
= 0x00000000,
133 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
134 .grp_addds
= 0x00000030,
135 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
136 .grp_ctlds
= 0x00000030,
137 /* DATA[00:63]: Differential input, 40 ohm */
138 .grp_ddrmode
= 0x00020000,
139 .grp_b0ds
= 0x00000030,
140 .grp_b1ds
= 0x00000030,
141 .grp_b2ds
= 0x00000030,
142 .grp_b3ds
= 0x00000030,
143 .grp_b4ds
= 0x00000030,
144 .grp_b5ds
= 0x00000030,
145 .grp_b6ds
= 0x00000030,
146 .grp_b7ds
= 0x00000030,
149 /* MT41K64M16JT-125 (1Gb density) */
150 static struct mx6_ddr3_cfg mt41k64m16jt_125
= {
163 /* MT41K128M16JT-125 (2Gb density) */
164 static struct mx6_ddr3_cfg mt41k128m16jt_125
= {
177 /* MT41K256M16HA-125 (4Gb density) */
178 static struct mx6_ddr3_cfg mt41k256m16ha_125
= {
192 * calibration - these are the various CPU/DDR3 combinations we support
194 static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib
= {
195 /* write leveling calibration determine */
196 .p0_mpwldectrl0
= 0x004C004E,
197 .p0_mpwldectrl1
= 0x00440044,
198 /* Read DQS Gating calibration */
199 .p0_mpdgctrl0
= 0x42440247,
200 .p0_mpdgctrl1
= 0x02310232,
201 /* Read Calibration: DQS delay relative to DQ read access */
202 .p0_mprddlctl
= 0x45424746,
203 /* Write Calibration: DQ/DM delay relative to DQS write access */
204 .p0_mpwrdlctl
= 0x33382C31,
207 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib
= {
208 /* write leveling calibration determine */
209 .p0_mpwldectrl0
= 0x001B0016,
210 .p0_mpwldectrl1
= 0x000C000E,
211 /* Read DQS Gating calibration */
212 .p0_mpdgctrl0
= 0x4324033A,
213 .p0_mpdgctrl1
= 0x00000000,
214 /* Read Calibration: DQS delay relative to DQ read access */
215 .p0_mprddlctl
= 0x40403438,
216 /* Write Calibration: DQ/DM delay relative to DQS write access */
217 .p0_mpwrdlctl
= 0x40403D36,
220 static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib
= {
221 /* write leveling calibration determine */
222 .p0_mpwldectrl0
= 0x00420043,
223 .p0_mpwldectrl1
= 0x0016001A,
224 /* Read DQS Gating calibration */
225 .p0_mpdgctrl0
= 0x4238023B,
226 .p0_mpdgctrl1
= 0x00000000,
227 /* Read Calibration: DQS delay relative to DQ read access */
228 .p0_mprddlctl
= 0x40404849,
229 /* Write Calibration: DQ/DM delay relative to DQS write access */
230 .p0_mpwrdlctl
= 0x40402E2F,
233 static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib
= {
234 /* write leveling calibration determine */
235 .p0_mpwldectrl0
= 0x00190017,
236 .p0_mpwldectrl1
= 0x00140026,
237 /* Read DQS Gating calibration */
238 .p0_mpdgctrl0
= 0x43380347,
239 .p0_mpdgctrl1
= 0x433C034D,
240 /* Read Calibration: DQS delay relative to DQ read access */
241 .p0_mprddlctl
= 0x3C313539,
242 /* Write Calibration: DQ/DM delay relative to DQS write access */
243 .p0_mpwrdlctl
= 0x36393C39,
246 static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib
= {
247 /* write leveling calibration determine */
248 .p0_mpwldectrl0
= 0x003C003C,
249 .p0_mpwldectrl1
= 0x001F002A,
250 /* Read DQS Gating calibration */
251 .p0_mpdgctrl0
= 0x42410244,
252 .p0_mpdgctrl1
= 0x4234023A,
253 /* Read Calibration: DQS delay relative to DQ read access */
254 .p0_mprddlctl
= 0x484A4C4B,
255 /* Write Calibration: DQ/DM delay relative to DQS write access */
256 .p0_mpwrdlctl
= 0x33342B32,
259 static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib
= {
260 /* write leveling calibration determine */
261 .p0_mpwldectrl0
= 0x00190017,
262 .p0_mpwldectrl1
= 0x00140026,
263 .p1_mpwldectrl0
= 0x0021001C,
264 .p1_mpwldectrl1
= 0x0011001D,
265 /* Read DQS Gating calibration */
266 .p0_mpdgctrl0
= 0x43380347,
267 .p0_mpdgctrl1
= 0x433C034D,
268 .p1_mpdgctrl0
= 0x032C0324,
269 .p1_mpdgctrl1
= 0x03310232,
270 /* Read Calibration: DQS delay relative to DQ read access */
271 .p0_mprddlctl
= 0x3C313539,
272 .p1_mprddlctl
= 0x37343141,
273 /* Write Calibration: DQ/DM delay relative to DQS write access */
274 .p0_mpwrdlctl
= 0x36393C39,
275 .p1_mpwrdlctl
= 0x42344438,
278 static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib
= {
279 /* write leveling calibration determine */
280 .p0_mpwldectrl0
= 0x003C003C,
281 .p0_mpwldectrl1
= 0x001F002A,
282 .p1_mpwldectrl0
= 0x00330038,
283 .p1_mpwldectrl1
= 0x0022003F,
284 /* Read DQS Gating calibration */
285 .p0_mpdgctrl0
= 0x42410244,
286 .p0_mpdgctrl1
= 0x4234023A,
287 .p1_mpdgctrl0
= 0x022D022D,
288 .p1_mpdgctrl1
= 0x021C0228,
289 /* Read Calibration: DQS delay relative to DQ read access */
290 .p0_mprddlctl
= 0x484A4C4B,
291 .p1_mprddlctl
= 0x4B4D4E4B,
292 /* Write Calibration: DQ/DM delay relative to DQS write access */
293 .p0_mpwrdlctl
= 0x33342B32,
294 .p1_mpwrdlctl
= 0x3933332B,
297 static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib
= {
298 /* write leveling calibration determine */
299 .p0_mpwldectrl0
= 0x001E001A,
300 .p0_mpwldectrl1
= 0x0026001F,
301 /* Read DQS Gating calibration */
302 .p0_mpdgctrl0
= 0x43370349,
303 .p0_mpdgctrl1
= 0x032D0327,
304 /* Read Calibration: DQS delay relative to DQ read access */
305 .p0_mprddlctl
= 0x3D303639,
306 /* Write Calibration: DQ/DM delay relative to DQS write access */
307 .p0_mpwrdlctl
= 0x32363934,
310 static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib
= {
311 /* write leveling calibration determine */
312 .p0_mpwldectrl0
= 0X00480047,
313 .p0_mpwldectrl1
= 0X003D003F,
314 /* Read DQS Gating calibration */
315 .p0_mpdgctrl0
= 0X423E0241,
316 .p0_mpdgctrl1
= 0X022B022C,
317 /* Read Calibration: DQS delay relative to DQ read access */
318 .p0_mprddlctl
= 0X49454A4A,
319 /* Write Calibration: DQ/DM delay relative to DQS write access */
320 .p0_mpwrdlctl
= 0X2E372C32,
323 static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib
= {
324 /* write leveling calibration determine */
325 .p0_mpwldectrl0
= 0X00220021,
326 .p0_mpwldectrl1
= 0X00200030,
327 .p1_mpwldectrl0
= 0X002D0027,
328 .p1_mpwldectrl1
= 0X00150026,
329 /* Read DQS Gating calibration */
330 .p0_mpdgctrl0
= 0x43330342,
331 .p0_mpdgctrl1
= 0x0339034A,
332 .p1_mpdgctrl0
= 0x032F0325,
333 .p1_mpdgctrl1
= 0x032F022E,
334 /* Read Calibration: DQS delay relative to DQ read access */
335 .p0_mprddlctl
= 0X3A2E3437,
336 .p1_mprddlctl
= 0X35312F3F,
337 /* Write Calibration: DQ/DM delay relative to DQS write access */
338 .p0_mpwrdlctl
= 0X33363B37,
339 .p1_mpwrdlctl
= 0X40304239,
342 static void spl_dram_init(int width
, int size_mb
, int board_model
)
344 struct mx6_ddr3_cfg
*mem
= NULL
;
345 struct mx6_mmdc_calibration
*calib
= NULL
;
346 struct mx6_ddr_sysinfo sysinfo
= {
347 /* width of data bus:0=16,1=32,2=64 */
349 /* config for full 4GB range so that get_mem_size() works */
350 .cs_density
= 32, /* 32Gb per CS */
351 /* single chip select */
354 .rtt_wr
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
355 #ifdef RTT_NOM_120OHM
356 .rtt_nom
= 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
358 .rtt_nom
= 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
360 .walat
= 1, /* Write additional latency */
361 .ralat
= 5, /* Read additional latency */
362 .mif3_mode
= 3, /* Command prediction working mode */
363 .bi_on
= 1, /* Bank interleaving enabled */
364 .sde_to_rst
= 0x10, /* 14 cycles, 200us (JEDEC default) */
365 .rst_to_cke
= 0x23, /* 33 cycles, 500us (JEDEC default) */
366 .pd_fast_exit
= 1, /* enable precharge power-down fast exit */
370 * MMDC Calibration requires the following data:
371 * mx6_mmdc_calibration - board-specific calibration (routing delays)
372 * these calibration values depend on board routing, SoC, and DDR
373 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
374 * mx6_ddr_cfg - chip specific timing/layout details
376 if (width
== 16 && size_mb
== 128) {
377 mem
= &mt41k64m16jt_125
;
378 if (is_cpu_type(MXC_CPU_MX6Q
))
381 calib
= &mx6sdl_64x16_mmdc_calib
;
382 debug("1gB density\n");
383 } else if (width
== 16 && size_mb
== 256) {
384 /* 1x 2Gb density chip - same calib as 2x 2Gb */
385 mem
= &mt41k128m16jt_125
;
386 if (is_cpu_type(MXC_CPU_MX6Q
))
387 calib
= &mx6dq_128x32_mmdc_calib
;
389 calib
= &mx6sdl_128x32_mmdc_calib
;
390 debug("2gB density\n");
391 } else if (width
== 16 && size_mb
== 512) {
392 mem
= &mt41k256m16ha_125
;
393 if (is_cpu_type(MXC_CPU_MX6Q
))
394 calib
= &mx6dq_256x16_mmdc_calib
;
396 calib
= &mx6sdl_256x16_mmdc_calib
;
397 debug("4gB density\n");
398 } else if (width
== 32 && size_mb
== 256) {
399 /* Same calib as width==16, size==128 */
400 mem
= &mt41k64m16jt_125
;
401 if (is_cpu_type(MXC_CPU_MX6Q
))
404 calib
= &mx6sdl_64x16_mmdc_calib
;
405 debug("1gB density\n");
406 } else if (width
== 32 && size_mb
== 512) {
407 mem
= &mt41k128m16jt_125
;
408 if (is_cpu_type(MXC_CPU_MX6Q
))
409 calib
= &mx6dq_128x32_mmdc_calib
;
411 calib
= &mx6sdl_128x32_mmdc_calib
;
412 debug("2gB density\n");
413 } else if (width
== 32 && size_mb
== 1024) {
414 mem
= &mt41k256m16ha_125
;
415 if (is_cpu_type(MXC_CPU_MX6Q
))
416 calib
= &mx6dq_256x32_mmdc_calib
;
418 calib
= &mx6sdl_256x32_mmdc_calib
;
419 debug("4gB density\n");
420 } else if (width
== 64 && size_mb
== 512) {
421 mem
= &mt41k64m16jt_125
;
422 debug("1gB density\n");
423 } else if (width
== 64 && size_mb
== 1024) {
424 mem
= &mt41k128m16jt_125
;
425 if (is_cpu_type(MXC_CPU_MX6Q
))
426 calib
= &mx6dq_128x64_mmdc_calib
;
428 calib
= &mx6sdl_128x64_mmdc_calib
;
429 debug("2gB density\n");
430 } else if (width
== 64 && size_mb
== 2048) {
431 mem
= &mt41k256m16ha_125
;
432 if (is_cpu_type(MXC_CPU_MX6Q
))
433 calib
= &mx6dq_256x64_mmdc_calib
;
434 debug("4gB density\n");
437 if (!(mem
&& calib
)) {
438 puts("Error: Invalid Calibration/Board Configuration\n");
439 printf("MEM : %s\n", mem
? "OKAY" : "NULL");
440 printf("CALIB : %s\n", calib
? "OKAY" : "NULL");
441 printf("CPUTYPE: %s\n",
442 is_cpu_type(MXC_CPU_MX6Q
) ? "IMX6Q" : "IMX6DL");
443 printf("SIZE_MB: %d\n", size_mb
);
444 printf("WIDTH : %d\n", width
);
448 if (is_cpu_type(MXC_CPU_MX6Q
))
449 mx6dq_dram_iocfg(width
, &mx6dq_ddr_ioregs
,
452 mx6sdl_dram_iocfg(width
, &mx6sdl_ddr_ioregs
,
454 mx6_dram_cfg(&sysinfo
, calib
, mem
);
457 static void ccgr_init(void)
459 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
461 writel(0x00C03F3F, &ccm
->CCGR0
);
462 writel(0x0030FC03, &ccm
->CCGR1
);
463 writel(0x0FFFC000, &ccm
->CCGR2
);
464 writel(0x3FF00000, &ccm
->CCGR3
);
465 writel(0xFFFFF300, &ccm
->CCGR4
); /* enable NAND/GPMI/BCH clks */
466 writel(0x0F0000C3, &ccm
->CCGR5
);
467 writel(0x000003FF, &ccm
->CCGR6
);
470 static void gpr_init(void)
472 struct iomuxc
*iomux
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
474 /* enable AXI cache for VDOA/VPU/IPU */
475 writel(0xF00000CF, &iomux
->gpr
[4]);
476 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
477 writel(0x007F007F, &iomux
->gpr
[6]);
478 writel(0x007F007F, &iomux
->gpr
[7]);
482 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
483 * - we have a stack and a place to store GD, both in SRAM
484 * - no variable global data is available
486 void board_init_f(ulong dummy
)
488 struct ventana_board_info ventana_info
;
491 /* setup clock gating */
494 /* setup AIPS and disable watchdog */
500 /* iomux and setup of i2c */
507 /* UART clocks enabled and gd valid - init serial console */
508 preloader_console_init();
510 /* read/validate EEPROM info to determine board model and SDRAM cfg */
511 board_model
= read_eeprom(CONFIG_I2C_GSC
, &ventana_info
);
513 /* configure model-specific gpio */
514 setup_iomux_gpio(board_model
, &ventana_info
);
516 /* provide some some default: 32bit 128MB */
517 if (GW_UNKNOWN
== board_model
) {
518 ventana_info
.sdram_width
= 2;
519 ventana_info
.sdram_size
= 3;
522 /* configure MMDC for SDRAM width/size and per-model calibration */
523 spl_dram_init(8 << ventana_info
.sdram_width
,
524 16 << ventana_info
.sdram_size
,
528 memset(__bss_start
, 0, __bss_end
- __bss_start
);
530 /* disable boot watchdog */
531 gsc_boot_wd_disable();
534 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
535 /* its our chance to print info about boot device */
536 void spl_board_init(void)
538 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
539 u32 boot_device
= spl_boot_device();
541 switch (boot_device
) {
542 case BOOT_DEVICE_MMC1
:
543 puts("Booting from MMC\n");
545 case BOOT_DEVICE_NAND
:
546 puts("Booting from NAND\n");
548 case BOOT_DEVICE_SATA
:
549 puts("Booting from SATA\n");
552 puts("Unknown boot device\n");
556 void reset_cpu(ulong addr
)