board/gateworks/venice/venice.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2021 Gateworks Corporation
   4  */
   5
   6 #include <fdt_support.h>
   7 #include <init.h>
   8 #include <led.h>
   9 #include <mmc.h>
  10 #include <miiphy.h>
  11 #include <mmc.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/sys_proto.h>
  14 #include <asm/mach-imx/boot_mode.h>
  15
  16 #include "eeprom.h"
  17
  18 int board_phys_sdram_size(phys_size_t *size)
  19 {
  20         if (!size)
  21                 return -EINVAL;
  22
  23         *size = get_ram_size((void *)PHYS_SDRAM, (long)PHYS_SDRAM_SIZE + (long)PHYS_SDRAM_2_SIZE);
  24
  25         return 0;
  26 }
  27
  28 int board_fit_config_name_match(const char *name)
  29 {
  30         int i  = 0;
  31         const char *dtb;
  32         static char init;
  33         char buf[32];
  34
  35         do {
  36                 dtb = eeprom_get_dtb_name(i++, buf, sizeof(buf));
  37                 if (!strcmp(dtb, name)) {
  38                         if (!init++)
  39                                 printf("DTB     : %s\n", name);
  40                         return 0;
  41                 }
  42         } while (dtb);
  43
  44         return -1;
  45 }
  46
  47 static int __maybe_unused setup_fec(void)
  48 {
  49         struct iomuxc_gpr_base_regs *gpr =
  50                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  51
  52 #ifndef CONFIG_IMX8MP
  53         /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  54         clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
  55 #else
  56         /* Enable RGMII TX clk output */
  57         setbits_le32(&gpr->gpr[1], BIT(22));
  58 #endif
  59
  60         return 0;
  61 }
  62
  63 #if (IS_ENABLED(CONFIG_NET))
  64 int board_phy_config(struct phy_device *phydev)
  65 {
  66         unsigned short val;
  67
  68         switch (phydev->phy_id) {
  69         case 0x2000a231: /* TI DP83867 GbE PHY */
  70                 puts("DP83867 ");
  71                 /* LED configuration */
  72                 val = 0;
  73                 val |= 0x5 << 4; /* LED1(Amber;Speed)   : 1000BT link */
  74                 val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
  75                 phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
  76                 break;
  77         }
  78
  79         if (phydev->drv->config)
  80                 phydev->drv->config(phydev);
  81
  82         return 0;
  83 }
  84 #endif // IS_ENABLED(CONFIG_NET)
  85
  86 int board_init(void)
  87 {
  88         venice_eeprom_init(1);
  89
  90         if (IS_ENABLED(CONFIG_FEC_MXC))
  91                 setup_fec();
  92
  93         return 0;
  94 }
  95
  96 int board_late_init(void)
  97 {
  98         const char *str;
  99         struct mmc *mmc = NULL;
 100         char env[32];
 101         int ret, i;
 102         u8 enetaddr[6];
 103         char fdt[64];
 104         int bootdev;
 105
 106         /* Set board serial/model */
 107         if (!env_get("serial#"))
 108                 env_set_ulong("serial#", eeprom_get_serial());
 109         env_set("model", eeprom_get_model());
 110
 111         /* Set fdt_file vars */
 112         i = 0;
 113         do {
 114                 str = eeprom_get_dtb_name(i, fdt, sizeof(fdt));
 115                 if (str) {
 116                         sprintf(env, "fdt_file%d", i + 1);
 117                         strcat(fdt, ".dtb");
 118                         env_set(env, fdt);
 119                 }
 120                 i++;
 121         } while (str);
 122
 123         /* Set mac addrs */
 124         i = 0;
 125         do {
 126                 if (i)
 127                         sprintf(env, "eth%daddr", i);
 128                 else
 129                         sprintf(env, "ethaddr");
 130                 str = env_get(env);
 131                 if (!str) {
 132                         ret = eeprom_getmac(i, enetaddr);
 133                         if (!ret)
 134                                 eth_env_set_enetaddr(env, enetaddr);
 135                 }
 136                 i++;
 137         } while (!ret);
 138
 139         /*
 140          * set bootdev/bootblk/bootpart (used in firmware_update script)
 141          * dynamically depending on boot device and SoC
 142          */
 143         bootdev = -1;
 144         switch (get_boot_device()) {
 145         case SD1_BOOT:
 146         case MMC1_BOOT: /* SDHC1 */
 147                 bootdev = 0;
 148                 break;
 149         case SD2_BOOT:
 150         case MMC2_BOOT: /* SDHC2 */
 151                 bootdev = 1;
 152                 break;
 153         case SD3_BOOT:
 154         case MMC3_BOOT: /* SDHC3 */
 155                 bootdev = 2;
 156                 break;
 157         default:
 158                 bootdev = 2; /* assume SDHC3 (eMMC) if booting over SDP */
 159                 break;
 160         }
 161         if (bootdev != -1)
 162                 mmc = find_mmc_device(bootdev);
 163         if (mmc) {
 164                 int bootblk;
 165
 166                 if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
 167                         bootblk = 32 * SZ_1K / 512;
 168                 else
 169                         bootblk = 33 * SZ_1K / 512;
 170                 mmc_init(mmc);
 171                 if (!IS_SD(mmc)) {
 172                         int bootpart;
 173
 174                         switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
 175                         case 1: /* boot0 */
 176                                 bootpart = 1;
 177                                 break;
 178                         case 2: /* boot1 */
 179                                 bootpart = 2;
 180                                 break;
 181                         case 7: /* user */
 182                         default:
 183                                 bootpart = 0;
 184                                 break;
 185                         }
 186                         /* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */
 187                         if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) &&
 188                             (bootpart == 1 || bootpart == 2))
 189                                 bootblk = 0;
 190                         env_set_hex("bootpart", bootpart);
 191                         env_set_hex("bootblk", bootblk);
 192                 } else { /* SD */
 193                         env_set("bootpart", "");
 194                         env_set_hex("bootblk", bootblk);
 195                 }
 196                 env_set_hex("dev", bootdev);
 197         }
 198
 199         /* override soc=imx8m to provide a more specific soc name */
 200         if (IS_ENABLED(CONFIG_IMX8MN))
 201                 env_set("soc", "imx8mn");
 202         else if (IS_ENABLED(CONFIG_IMX8MP))
 203                 env_set("soc", "imx8mp");
 204         else if (IS_ENABLED(CONFIG_IMX8MM))
 205                 env_set("soc", "imx8mm");
 206
 207         return 0;
 208 }
 209
 210 int board_mmc_get_env_dev(int devno)
 211 {
 212         return devno;
 213 }
 214
 215 uint mmc_get_env_part(struct mmc *mmc)
 216 {
 217         if (!IS_SD(mmc)) {
 218                 switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
 219                 case 1:
 220                         return 1;
 221                 case 2:
 222                         return 2;
 223                 }
 224         }
 225
 226         return 0;
 227 }
 228
 229 int ft_board_setup(void *fdt, struct bd_info *bd)
 230 {
 231         const char *base_model = eeprom_get_baseboard_model();
 232         char pcbrev;
 233         int off;
 234
 235         /* set board model dt prop */
 236         fdt_setprop_string(fdt, 0, "board", eeprom_get_model());
 237
 238         if (!strncmp(base_model, "GW73", 4)) {
 239                 pcbrev = get_pcb_rev(base_model);
 240
 241                 if (pcbrev > 'B' && pcbrev < 'E') {
 242                         printf("adjusting dt for %s\n", base_model);
 243
 244                         /*
 245                          * revC/D/E has PCIe 4-port switch which changes
 246                          * ethernet1 PCIe GbE:
 247                          * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0
 248                          *   to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0
 249                          */
 250                         off = fdt_path_offset(fdt, "ethernet1");
 251                         if (off > 0) {
 252                                 u32 reg[5];
 253
 254                                 fdt_set_name(fdt, off, "pcie@5,0");
 255                                 off = fdt_parent_offset(fdt, off);
 256                                 fdt_set_name(fdt, off, "pcie@2,3");
 257                                 memset(reg, 0, sizeof(reg));
 258                                 reg[0] = cpu_to_fdt32(PCI_DEVFN(3, 0));
 259                                 fdt_setprop(fdt, off, "reg", reg, sizeof(reg));
 260                         }
 261                 }
 262         }
 263
 264         return 0;
 265 }