3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/ppc4xx-gpio.h>
32 #include <gdsys_fpga.h>
34 #define PHYREG_CONTROL 0
35 #define PHYREG_PAGE_ADDRESS 22
36 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
37 #define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
40 UNITTYPE_CCD_SWITCH
= 1,
50 int configure_gbit_phy(unsigned char addr
)
55 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
56 PHYREG_PAGE_ADDRESS
, 0x0002))
58 /* disable SGMII autonegotiation */
59 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
60 PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2
, 0x800a))
63 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
64 PHYREG_PAGE_ADDRESS
, 0x0000))
66 /* switch from powerdown to normal operation */
67 if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
68 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1
, &value
))
70 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
71 PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1
, value
& ~0x0004))
73 /* reset phy so settings take effect */
74 if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME
, addr
,
75 PHYREG_CONTROL
, 0x9140))
81 printf("Error writing to the PHY addr=%02x\n", addr
);
86 * Check Board Identity:
90 ihs_fpga_t
*fpga
= (ihs_fpga_t
*) CONFIG_SYS_FPGA_BASE(0);
91 char *s
= getenv("serial#");
92 u16 versions
= in_le16(&fpga
->versions
);
93 u16 fpga_version
= in_le16(&fpga
->fpga_version
);
94 u16 fpga_features
= in_le16(&fpga
->fpga_features
);
96 unsigned hardware_version
;
97 unsigned feature_channels
;
98 unsigned feature_expansion
;
100 unit_type
= (versions
& 0xf000) >> 12;
101 hardware_version
= versions
& 0x000f;
102 feature_channels
= fpga_features
& 0x007f;
103 feature_expansion
= fpga_features
& (1<<15);
107 printf("CATCenter Io");
116 case UNITTYPE_CCD_SWITCH
:
117 printf("CCD-Switch");
121 printf("UnitType %d(not supported)", unit_type
);
125 switch (hardware_version
) {
127 printf(" HW-Ver 1.00\n");
131 printf(" HW-Ver 1.10\n");
135 printf(" HW-Ver 1.21\n");
139 printf(" HW-Ver 1.22\n");
143 printf(" HW-Ver %d(not supported)\n",
148 printf(" FPGA V %d.%02d, features:",
149 fpga_version
/ 100, fpga_version
% 100);
151 printf(" %d channel(s)", feature_channels
);
153 printf(", expansion %ssupported\n", feature_expansion
? "" : "un");
161 int last_stage_init(void)
163 ihs_fpga_t
*fpga
= (ihs_fpga_t
*) CONFIG_SYS_FPGA_BASE(0);
166 miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME
,
167 bb_miiphy_read
, bb_miiphy_write
);
169 for (k
= 0; k
< 32; ++k
)
170 configure_gbit_phy(k
);
172 /* take fpga serdes blocks out of reset */
173 out_le16(&fpga
->quad_serdes_reset
, 0);